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Organization

Arizona State University
Contributors
Edward Andert
Aman Arora
Ayan Banerjee
Hans Behrens
Sumukh Bhanushali
Chaitali Chakrabarti
Vidya A. Chhabria
Chetan Choppali Sudarshan
Amol Gaidhane
Jiaqi Gu
Sandeep Gupta
John Gustafson
Fengyang Jiang
Sumedh Joshi
Imane Lamrani
Haotian Lu
Debnath Maiti
Aranyak Maity
Francis Mendoza
Arindam Sanyal
Aviral Shrivastava
Aviral Shrivastava
Gian Singh
Hwisoo So
Amitesh Sridharan
Jingbo Sun
Sarma Vrudhula
Zhenyu Wang
Hua Wei
Jeff Zhang
Jeff Zhang
Session Chairs
Vidya Chhabria
Hokeun Kim
Presentations
Work-in-Progress Poster
A DRAM-based PIM Architecture for Accelerated and Energy-Efficient Execution of Transformers
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Work-in-Progress Poster
Adaptive Graph Learning for Efficient Thermal Analysis of the Chiplet System under Interface Variations
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Work-in-Progress Poster
Addressing the Diversity in AI Computing: An On-chip Programmable Accelerator
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Research Manuscript
Algorithm-Hardware Co-Design of Distribution-Aware Logarithmic-Posit Encodings for Efficient DNN Inference
AI
AI/ML Algorithms
Work-in-Progress Poster
Analytical Modeling and Electro-Thermal Benchmarking of 2.5D/3D Heterogeneous Integration for AI Computing
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Research Manuscript
Conclave - Secure and Robust Cooperative Perception for Connected Autonomous Vehicle Using Authenticated Consensus and Trust Scoring
Autonomous Systems
Autonomous Systems (Automotive, Robotics, Drones)
Work-in-Progress Poster
Cooling the Chaos: Mitigating the Effect of Threshold Voltage Variation in Cryogenic CMOS Memories
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Workshop
DCgAA 2024: International Workshop on DL-Hardware Co-Design for Generative AI Acceleration
AI
Tutorial
Design and Synthesis of Certifiably Safe AI-enabled Autonomy with Focus on Human-in-the-Loop Human-in-the Plant Systems
AI
Work-in-Progress Poster
DOCTOR: Dynamic On-Chip Remediation Against Temporally-Drifting Thermal Variations Toward Self-Corrected Photonic Tensor Accelerators
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Research Manuscript
Efficient Memory Integration: MRAM-SRAM Hybrid Accelerator for Sparse On-Device Learning
Design
In-memory and Near-memory Computing Architectures, Applications and Systems
Research Manuscript
Field Programmable Quantum Array Compilation with Flying Ancillas
Design
Quantum Computing
Tutorial
Flash – An Overlooked Technology in VLSI Design
Design
Research Panel
Generative AI for Chip Design: Game Changer or Damp Squib?
AI
EDA
Research Manuscript
GreenFPGA: Evaluating FPGAs as Environmentally Sustainable Computing Solutions
EDA
Test, Validation and Silicon Lifecycle Management
Late Breaking Results Poster
Late Breaking Results: Machine Learning Based Reference Ripple Error Suppression in Successive Approximation Register Analog-to-Digital Converters
Research Manuscript
Maintaining Sanity: Algorithm-based Comprehensive Fault Tolerance for CNNs
Embedded Systems
Time-Critical and Fault-Tolerant System Design
Work-in-Progress Poster
Operational Safety in Human-in-the-loop Human-in-the-plant Autonomous Systems
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Work-in-Progress Poster
RobustState: Boosting Fidelity of Quantum State Preparation via Noise-Aware Variational Training
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Work-in-Progress Poster
Transformer-QEC: Quantum Error Correction Code Decoding with Transferable Transformers
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Research Manuscript
zeroTT: A Two-Step State Transition Avoidance Scheme for MLC STT-RAM
Embedded Systems
Embedded Memory and Storage Systems
Sessions
Research Manuscript
Challenging the Autonomy Challenges
Autonomous Systems
Autonomous Systems (Automotive, Robotics, Drones)
Research Manuscript
SPeeDY: Innovative Strategies for Synthesis, Placement, DRC, and Yield
EDA
Physical Design and Verification