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Organization

NVIDIA
Contributors
Anthony Agnesina
Michael Andersch
Sanmitra Banerjee
Michael Boone
Federico Busato
Bryan Catanzaro
Emmanuel Chao
Sanjay Choudhry
Sid Dhodhi
Sukru Eryilmaz
Ankit Kumar Garg
Saad Godil
Brucek Khailany
Robert Kirby
Rundong Li
Rongjian Liang
Chengcheng Liu
Mingjie Liu
Michal Marcinkiewicz
Arkadiusz Nowaczynski
Baskar Rajagopalan
Anand Rajaram
Haoxing Ren
Rajarshi Roy
Santosh Santosh
Ambar Sarkar
Jialin Song
Yifei Song
YunDa Tsai
Anusha Vemuri
Jie Xin
Qikun Xue
Haoyu Yang
June Yang
Yanqing Zhang
Feiwen Zhu
Session Chairs
Haoxing “Mark” Ren
Charbel Sakr
Presentations
Front-End Design
AI co-pilot: Exploring the AI Frontier in Chip Design
AI
Design
Engineering Tracks
Front-End Design
Front-End Design
AI-Powered High-Sigma Automated Full Library Verification Methodology for Standard Cells
AI
Design
Engineering Tracks
Front-End Design
Research Manuscript
Automatically Fixing RTL Syntax Errors with Large Language Model
AI
AI/ML Application and Infrastructure
Research Manuscript
CAMO: Correlation-Aware Mask Optimization with Modulated Reinforcement Learning
Design
Design for Manufacturability and Reliability
Research Manuscript
CircuitVAE: Efficient and Scalable Latent Circuit Optimization
EDA
RTL/Logic Level and High-level Synthesis
Research Manuscript
DGR: Differentiable Global Router
EDA
Physical Design and Verification
Work-in-Progress Poster
DOCTOR: Dynamic On-Chip Remediation Against Temporally-Drifting Thermal Variations Toward Self-Corrected Photonic Tensor Accelerators
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Embedded Systems and Software
Edge Intelligence & GenAI: Exploring Challenges and Ethics
AI
Embedded Systems
Engineering Tracks
Engineering Track Poster
Forward Progress Testing: Saftey vs Liveness Assertion
Back-End Design
Embedded Systems
Front-End Design
IP
Work-in-Progress Poster
GL0AM: GPU Logic Simulation Using 0-Delay and Re-simulation Acceleration Method
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Engineering Track Poster
GPU Accelerated Harmonic Balance SPICE Simulation
Back-End Design
Embedded Systems
Front-End Design
IP
Work-in-Progress Poster
GPU-Accelerated BFS for Dynamic Networks
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Exhibitor Forum
Leveraging AI/ML for Electronic Design and Simulation
Research Manuscript
ScaleFold: Reducing AlphaFold Initial Training Time to 10 Hours
AI
AI/ML Application and Infrastructure
Engineering Track Poster
SigmaDVD: High Coverage Solution for Power Integrity Signoff
Back-End Design
Embedded Systems
Front-End Design
IP
Exhibitor Forum
Visualizing the Future of Multi-die Design with Ansys & NVIDIA Omniverse
Front-End Design
What is the Future of Design Verification? UVM, PSS, Formal, VIP, AI & Beyond
AI
Design
Engineering Tracks
Front-End Design
Sessions
Research Manuscript
It's Not 8b Retro-Gaming, It's State-Of-The-Art Architectures Using Quantization, Sparsity, and Compression!
AI
Design
AI/ML Architecture Design
Research Manuscript
Foundation Models for EDA and Beyond
AI
AI/ML Application and Infrastructure