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Organization

The Chinese University of Hong Kong
Contributors
Chen BAI
Guojin Chen
Shixin Chen
Zelin Du
Farzan Farnia
Rongliang Fu
Zhuolun He
Tsung-Yi Ho
Kecheng Huang
Zixuan Huang
Jiaxi Jiang
Shui Jiang
Beichen Li
Mingjun Li
Siyuan Liang
Peiyu Liao
Dahua Lin
Shiju Lin
Fangzhou Liu
Hongduo Liu
Tianji Liu
Yuan Pu
Zili Shao
Yang Sun
Zixiao WANG
Ziyi Wang
Martin Wong
Peng Xu
Jin Xue
Ming-Chang Yang
Xufeng Yao
Shuo Yin
Evangeline Young
Bei Yu
Xinyun Zhang
Yu Zhang
Wenqian Zhao
Su Zheng
Binwu Zhu
Keren Zhu
Lancheng Zou
Session Chairs
Evangeline Young
Presentations
Research Manuscript
A Holistic Functionalization Approach to Optimizing Imperative Tensor Programs in Deep Learning
AI
AI/ML Application and Infrastructure
Work-in-Progress Poster
An Effective Timing Driven Placement with Accurate Differentiable Timing Approximation Integration
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Research Manuscript
CAMO: Correlation-Aware Mask Optimization with Modulated Reinforcement Learning
Design
Design for Manufacturability and Reliability
Research Manuscript
ChatPattern: Layout Pattern Customization via Natural Language
Design
Design for Manufacturability and Reliability
Research Manuscript
Disentangle, Align and Generalize: Learning A Timing Predictor from Different Technology Nodes
EDA
Timing and Power Analysis and Optimization
Research Manuscript
Efficient Bilevel Source Mask Optimization
Design
Design for Manufacturability and Reliability
Research Manuscript
Efficient ILT via Multigrid-Schwartz Method
Design
Design for Manufacturability and Reliability
Research Manuscript
EMOGen: Enhancing Mask Optimization via Pattern Generation
Design
Design for Manufacturability and Reliability
Research Manuscript
Fracturing-aware Curvilinear ILT via Circular E-beam Mask Writer
Design
Design for Manufacturability and Reliability
Research Manuscript
G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner
Design
SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
GCS-Timer: GPU-Accelerated Current Source Model Based Static Timing Analysis
EDA
Timing and Power Analysis and Optimization
Research Manuscript
GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration
AI
AI/ML Algorithms
Research Manuscript
How to Steal CPU Idle Time When Synchronous I/O Mode Becomes Promising
Embedded Systems
Embedded Software
Research Manuscript
Ink: Efficient Incremental k-Critical Path Generation
EDA
Timing and Power Analysis and Optimization
Research Manuscript
Knowing The Spec to Explore The Design via Transformed Bayesian Optimization
EDA
RTL/Logic Level and High-level Synthesis
Research Manuscript
LaMUX: Optimized Logic-Gate-Enabled High-Performance Microfluidic Multiplexer Design
Design
Emerging Models of Computation
Late Breaking Results Poster
Late Breaking Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Integration (mLSI)
Research Manuscript
Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs
EDA
Physical Design and Verification
Research Manuscript
Massively Parallel AIG Resubstitution
EDA
RTL/Logic Level and High-level Synthesis
Research Manuscript
NeuroSelect: Learning to Select Clauses in SAT Solvers
EDA
Design Verification and Validation
Research Manuscript
PDRC: Package Design Rule Checking via GPU-Accelerated Geometric Intersection Algorithms for Non-Manhattan Geometry
EDA
Physical Design and Verification
Research Manuscript
Performance-driven Analog Routing via Heterogeneous 3DGNN and Potential Relaxation
EDA
Analog CAD, Simulation, Verification and Test
Research Manuscript
PipeSSD: A Lock-free Pipelined SSD Firmware Design for Multi-core Architecture
Embedded Systems
Embedded Memory and Storage Systems
Research Manuscript
RCGP: An Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits based on Efficient Cartesian Genetic Programming
Design
Quantum Computing
Research Manuscript
Size-Optimized Depth-Constrained Large Parallel Prefix Circuits
EDA
RTL/Logic Level and High-level Synthesis
Research Manuscript
Toward Controllable Hierarchical Clock Tree Synthesis with Skew-Latency-Load Tree
EDA
Physical Design and Verification
Research Manuscript
Unleashing the Potential of AQFP Logic Placement via Entanglement Entropy and Projection
EDA
Physical Design and Verification
Research Manuscript
WinoGen: A Highly Configurable Winograd Convolution IP Generator for Efficient CNN Acceleration on FPGA
Design
SoC, Heterogeneous, and Reconfigurable Architectures
Sessions
Research Manuscript
HLS & Emerging Techniques for Synthesis
EDA
RTL/Logic Level and High-level Synthesis