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Organization

Shenzhen University
Contributors
Ye Cai
Jiaxian Chen
Weijian Fan
Shaoqi Li
Huan Liu
Jiaxiang Liu
Jikang Liu
Zhuohua Liu
Chenlin Ma
Rui Mao
Haobin Tan
Tianyu Wang
Yi Wang
Jianan Yuan
Presentations
Research Manuscript
Every Failure Is A Lesson: Utilizing All Failure Samples To Deliver Tuning-Free Efficient Yield Evaluation
EDA
Physical Design and Verification
Research Manuscript
Formally Verifying Arithmetic Chisel Designs for All Bit Widths at Once
EDA
Design Verification and Validation
Research Manuscript
KATO: Knowledge Alignment And Transfer for Transistor Sizing Of Different Design and Technology
EDA
Analog CAD, Simulation, Verification and Test
Research Manuscript
Leanor: A Learning-Based Accelerator for Efficient Approximate Nearest Neighbor Search via Reduced Memory Access
AI
AI/ML Algorithms
Research Manuscript
Net Resource Allocation: A Desirable Initial Routing Step
EDA
Physical Design and Verification
Research Manuscript
PipeSSD: A Lock-free Pipelined SSD Firmware Design for Multi-core Architecture
Embedded Systems
Embedded Memory and Storage Systems
Research Manuscript
UpDLRM: Accelerating Personalized Recommendation using Real-World PIM Architecture
Design
In-memory and Near-memory Computing Architectures, Applications and Systems