Close

Organization

STMicroelectronics
Contributors
Chirag Agarwal
Frederic Avellaneda
Ankur Bal
Paola Baldrighi
MANISH BANSAL
Ambika Bhardwaj
Atul Bhargava
Edoardo Bollea
Michel Chevalier
Jules Coulon
Shoikat Das
Anuj Dhillon
Nicola DiCarolo
Marcello Dusini
Anil Dwivedi
Gabriele Faraone
Giovanna Franchino
Jean-Aranud Francois
Harsh Garg
Paras Garg
Rajnish GARG
Vaibhav Garg
Rohit Goel
Michelangelo Grosso
Roberto Guizzetti
Sharad Gupta
Shashank Gupta
Vijay Singh Khati
Ashish Kumar
Pallav Kumar
Rahul Kumar
ravinder kumar
Aradhana Kumari
Francois Lemery
Jerome Lescot
Dario Licastro
Andrea Lopinto
Mitu Mittal
Prachi Mrudula
Govind Pal
Anuradha Ray
Gianluca Rigano
Davide Sanalitro
Eugenio Serianni
Harshit Sharma
Amit Singh
Bhupendra Singh
Rajeev Singh
Piyush Soni
Saurabh Srivastava
kancou traore
Severin Trochut
Pascal Urard
Pawan Verma
Praveen Kumar Verma
Antoine Vialle
David Vincenzoni
Stephan Weber
Anil Yadav
Presentations
Engineering Track Poster
A New Approach to Efficient Prelim Package Generation for Faster SOC Implementation
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
A Novel Flow to Verify SoC Integration with Formal Property Verification
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Accelerating IO Liberty Generation through ML based Solution
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Achieving High Local Noise Coverage in Dynamic EMIR Analysis using SigmaDVD
Back-End Design
Embedded Systems
Front-End Design
IP
Work-in-Progress Poster
Advanced Analog Design Optimization: Comparison Between Reinforcement Learning and Heuristic Algorithms
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
IP
Advancing Power Signoff for High Speed ΔΣADC
Engineering Tracks
IP
IP
An All-Digital IP for Fast Correction of Time-skew Mismatch in Time-Interleaved Analog to Digital Converters for Communication Receivers
Engineering Tracks
IP
IP
An All-Digital Transient Filter IP for Serial Links
Engineering Tracks
IP
Engineering Track Poster
An Integrated Behavioral Modeling Method for Mixed Signal IPs
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Automated Place and Route based solution for Custom Blocks
Back-End Design
Embedded Systems
Front-End Design
IP
Back-End Design
Automatic Layout Symmetry Annotation via Graph Node Embeddings
Back-End Design
Design
Engineering Tracks
Engineering Track Poster
Autonomous Power Sequence validation solution for I/O using Solido Design Environment
Back-End Design
Embedded Systems
Front-End Design
IP
IP
Beyond Digital: Innovation in symbolic simulator to empower IO analog circuit validation
Engineering Tracks
IP
Engineering Track Poster
Challenges and Improvements in StandardCell OpenAccess Content for Analog Design
Back-End Design
Embedded Systems
Front-End Design
IP
IP
Considering Selective Resistance Extraction for Performance & Accuracy Trade-off for Memory IP Simulation
Engineering Tracks
IP
Engineering Track Poster
Early detection of low power related issues using formal verification
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Enhancing and accelerating Verification with ad-hoc Python scripting
Back-End Design
Embedded Systems
Front-End Design
IP
Front-End Design
Enhancing Quality and Reducing Verification Effort for RTL Implementations against High-Level C/C++ Models using Formal Equivalence
Design
Engineering Tracks
Front-End Design
IP
Fast and Deterministic Memory Yield Estimation Using Machine Learning Augmented Statistical Simulations
Engineering Tracks
IP
Engineering Track Poster
Faster Timing Closure of Multiple Power Domains Based Designs with SMVA
Back-End Design
Embedded Systems
Front-End Design
IP
IP
Low-Cost Built In Self Test IP for Nextgen Continuous Time Sigma Delta ADCs
Engineering Tracks
IP
Engineering Track Poster
Machine Learning-based feasibility estimation of digital blocks for improved productivity in Analog-on-Top Back-End design flows
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Novel Way of Checking and Analyzing Peak to Peak Voltage Variation Challenges for High Computational Multiprocessors SOC
Back-End Design
Embedded Systems
Front-End Design
IP
Back-End Design
Pruning Netlist: A Smarter Approach to Efficient and Reliable Circuit Characterization
Back-End Design
Design
Engineering Tracks
Engineering Track Poster
Quality Assurance of DRC deck for Devices by SKILL Automation
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Resolving the seed promotion due to device layers derivation
Back-End Design
Embedded Systems
Front-End Design
IP
IP
Window Feedback Based Multi-Master Arbiter IP for Efficient Hardware Resource Sharing
Engineering Tracks
IP