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High Confidence Hierarchical bottom-up DVD methodology for EMIR Signoff of Automotive SOCs
DescriptionLatest Design trends with advanced technology nodes have resulted in shrinking of Dynamic Voltage Drop margins. Traditionally in the ASIC design cycle, PDN signoff is executed after full chip integration is finalised. This makes design susceptible to potential unwarranted dynamic noise issues arising out of SOC integration and thereby presenting crucial challenges to any last minute surprises for Power Integrity closure.

This necessitates the requirement of a robust hierarchical dvd methodology which promises high confidence of real impact dvd violations at block level, less surprises in new IR violations moving to top, and also ensuring faster convergence cycles when running a full chip transient analysis.

In this paper, we present an accurate and efficient hierarchical dvd methodology which leverages use of smart load modelling and Event Replay technology on Ansys RedHawk SC platform. With this approach, 20% efficiency improvement has been observed in TAT and corelation of DVD Violations has been observed which otherwise was leading to ~25% extra DVD violations at SOC level.
Event Type
Back-End Design
TimeMonday, June 242:45pm - 3:00pm PDT
Location2008, 2nd Floor
Topics
Back-End Design
Design
Engineering Tracks