Presentation
Electromagnetic Solutions From Design to Sign-Off Stage For High-Speed SerDes Design
DescriptionIn high-speed SerDes design, to understand the EMag(electromagnetic) coupling between various elements of a high-frequency semiconductor device is very important, these EMag interactions include not only the silicon chip but also extend to the package that encloses it. At sign-off phase, it is common to find that block level pre-lvs EMag simulation result shows big difference when compare with measurement data, it is very necessary and important to perform EMag simulation at sign-off phase to reduce the gap.
Traditional EMag simulations method only consider chip coupling and not the packaging layers with on-chip metals model, that may lead to design specification violations. Traditional EMag flow only extract layout with passive devices, if EMag coupling is not fully considered, it will lead to a large mismatch between post-lvs simulation result and measurement.
In high-speed SerDes design, high-precision and high-efficiency electromagnetic modeling simulation is required to minimizing the associated EMag risks. RaptorH die+package modeling flow can predict the impact of EMag coupling with package layers at block stage; Exalto post-lvs EMag simulation can resolve mismatch between post-simulation and measurement at sign-off stage; and finally increase confidence in the performance of high-speed SerDes design.
Traditional EMag simulations method only consider chip coupling and not the packaging layers with on-chip metals model, that may lead to design specification violations. Traditional EMag flow only extract layout with passive devices, if EMag coupling is not fully considered, it will lead to a large mismatch between post-lvs simulation result and measurement.
In high-speed SerDes design, high-precision and high-efficiency electromagnetic modeling simulation is required to minimizing the associated EMag risks. RaptorH die+package modeling flow can predict the impact of EMag coupling with package layers at block stage; Exalto post-lvs EMag simulation can resolve mismatch between post-simulation and measurement at sign-off stage; and finally increase confidence in the performance of high-speed SerDes design.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP