Presentation
Microsoft's Comprehensive IP Handoff Flow
DescriptionMicrosoft addresses diverse IP challenges by prioritizing quality control for internal design teams, resolving handoff complexities, and managing 3rd party IPs with format inconsistencies. They emphasize early quality checks in design, acknowledging the rising cost of addressing IP issues later in the process, especially for intricate custom chips like Cobalt 100 and Maia 100.
To resolve these challenges, Microsoft has collaborated with Siemens to build and deploy a comprehensive IP QA framework covering database integrity, layout functionality equivalence, and validation of timing, power, noise parameters, and version-to-version IP QA. This framework integrates Siemens' Solido IP Validation into its Microsoft's CAD infrastructure.
This paper discusses how Microsoft's IP handoff flow automates and streamlines the entire process.
By catching potential issues much earlier in the design flow, the handoff flow has demonstrated remarkable results, saving approximately 2 weeks of engineering time. This not only contributes to substantial cost savings but also prevents the need for costly ECOs, leading to more predictable tapeout schedules.
To resolve these challenges, Microsoft has collaborated with Siemens to build and deploy a comprehensive IP QA framework covering database integrity, layout functionality equivalence, and validation of timing, power, noise parameters, and version-to-version IP QA. This framework integrates Siemens' Solido IP Validation into its Microsoft's CAD infrastructure.
This paper discusses how Microsoft's IP handoff flow automates and streamlines the entire process.
By catching potential issues much earlier in the design flow, the handoff flow has demonstrated remarkable results, saving approximately 2 weeks of engineering time. This not only contributes to substantial cost savings but also prevents the need for costly ECOs, leading to more predictable tapeout schedules.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP