Presentation
Reducing Interlayer misalignment caused by BLE (Bulk Layout Effect) : Solutions for improving in-chip uniformity of alignment between two layers
DescriptionAs DRAM devices continue to shrink, defects that are out of tolerance have become more prevalent. One such defect is interlayer misalignment, which occurs when two layers are not aligned correctly. Interlayer misalignment caused by the shifted patterns due to heat and stress is called as BLE (Bulk Layout Effect). It can lead to poor device yield.
In this paper, we propose two correction methods to reduce interlayer misalignment caused by BLE. The first method involves correcting the mask where BLE occurs in the opposite direction of the BLE. The second method involves correcting the other mask affected by BLE in the direction of the BLE. One of these methods should be chosen to ensure that it does not interfere with layout connections.
We evaluated methods using two different items. The interlayer misalignment in the chip decreased by 89% and 58% in item #1 and item #2, respectively. In addition, in-chip uniformity of alignment improved by 25% in item #1 and 27.4% in item #2.
It is proved that reducing interlayer misalignment caused by BLE can help improve in-chip uniformity of alignment. And it is expected to contribute to improving device yield by widening the window of manufacturing process tolerance.
In this paper, we propose two correction methods to reduce interlayer misalignment caused by BLE. The first method involves correcting the mask where BLE occurs in the opposite direction of the BLE. The second method involves correcting the other mask affected by BLE in the direction of the BLE. One of these methods should be chosen to ensure that it does not interfere with layout connections.
We evaluated methods using two different items. The interlayer misalignment in the chip decreased by 89% and 58% in item #1 and item #2, respectively. In addition, in-chip uniformity of alignment improved by 25% in item #1 and 27.4% in item #2.
It is proved that reducing interlayer misalignment caused by BLE can help improve in-chip uniformity of alignment. And it is expected to contribute to improving device yield by widening the window of manufacturing process tolerance.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP