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Struct Based Lower Level Modelling Using SystemVerilog UDT for Verification of Power Management IC
DescriptionIn this presentation, we introduce typical challenges encountered in the Digital Mixed-Signal (DMS) verification of a Power Management Integrated Circuit (PMIC), when its blocks are modelled in real number using High-Level Modelling (HLM) methodology. We talk about the traditional approach for modelling the PMIC blocks using SystemVerilog (SV) realnet using HLM, and mention the limitations of this approach. We propose a two faceted modelling methodology to overcome those limitations, viz., a) Creation of Lower Level Models (LLM) to account for more holistic verification in order to cover performance verification aspects, and ability to perform randomization and coverage, and b) Adoption of SV EEnet, a user-defined nettype in SV with ‘struct' datatype, with which we can model impedance dependent interaction between blocks. We thus illustrate the benefits of this SV-UVM compatible approach by showing how we could expand on the DMS verification checklist, thereby performing fully comprehensive functional and performance verification of the PMIC.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Topics
Back-End Design
Embedded Systems
Front-End Design
IP