Presentation
Memory Interface Architectures for Test Time Reduction in Zero DPPM SoCs
DescriptionThe semiconductor manufacturing process is far from perfect; therefore, testing is required to distinguish between functionally correct devices and devices that are defective due to production abnormalities. As the number of transistors on a die increases and more dies are added onto a board or into a package, it takes more time to test these devices. This, in turn, adds to the overall cost. Test time reduction is a critical step to reduce the overall cost of the device. On-chip memories have dominant footprint in today's SoCs. One of the SoCs with 650K flip flops shows that memories contribute to around 50% of total chip area. Memory tests are categorized into Memory Built-In Self-Test (MBIST) for internal memory defect detection and Ram Sequential ATPG for at-speed detection of faults around the memories. Test time for RAMs and ROMs is driven by the number of memories that get tested in parallel, which depends on the power grid budget of the SoCs. Multiple memories tested in parallel can increase the peak power dissipation, potentially generating excessive heat and causing device damage. The key challenge in generating good quality RAM sequential patterns with high test coverage and optimized test pattern count for memory dominated designs is degradation in the controllability on the memory inputs causing pattern inflation.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP