Presentation
Solving Memory Subsystem Verification Challenges for Multi-Instance Designs
DescriptionThis paper talks about the importance of the higher memory sub system level verification needs for protocol compliance of recent generation of memory sub systems using DDR like DDR5, Lpddr5 and how Cadence verification IP memory model team has come up/implemented a generic solution to describe such interconnect hierarchy in a modular and simple way. This approach defines a feature, associated grammar to capture memory sub system and implementation of handshake mechanism with triggers (like commands) to enhance individual instance DRAM model to be able to get visibility into other DRAM devices present in the design that are sharing resources like data bus, ZQ registers etc. Paper also given example of how this innovative solution has been used by Cadence memory controller IP and other external customers to enhance their sub system level verification to the next level while verifying protocol compliance for JEDEC define specification for multi-rank memory sub systems for DDR5 and Lpddr5 based designs. This solution can also potentially be applied to any Verification IP models to higher level protocol compliance checking.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP