Presentation
Unified Waveform Analysis Platform for Tr.-Level Design Verification
DescriptionThis paper presents a software tool designed to streamline the transistor-level design verification process. The tool excels in managing and integrating multiple waveform formats, such as Synopsys FSDB and Cadence TRN/VWDB, into a unified platform. This integration enhances the verification process's accuracy and speed. A Python-based API, along with a C++ hybrid approach, is utilized for ease of waveform manipulation and analysis. This tool overcomes the limitations of traditional verification methods in complex logic circuit designs, offering a more efficient and precise verification methodology.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP