Presentation
Automated Constraint Promotion Methodology from IP to SoC for Complex Designs
DescriptionIP cores require integration into top-level subsystems and/or SoCs. Writing constraints manually for top level design is prone to errors and difficult to verify and manage. This Synopsys webinar will cover how automated SDC constraints promotion from the IP to SoC level provides high-quality SDC relative to traditional manual time-consuming approaches. We will demonstrate the approach taken and benefits observed using automated constraints promotion and generation on an early PCIe® Gen 6 design resulting in shorter TAT and improved PPA. Lastly, we will illustrate how designers can ensure constraints correctness is maintained or bettered during the constraints promotion effort
Event Type
Engineering Track Poster
TimeTuesday, June 255:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP