Presentation
Advanced Static Methodology for Complete Connectivity and Glitch Signoff
DescriptionA chip design consists of interconnected blocks providing advanced functionality. While these blocks are thoroughly verified, the integrity of connections between these pre-verified components lacks clear ownership and efficient verification processes. With growing design complexity, the number of such connections can reach millions and lead to unexpected problems, which may appear late in the design flow. Therefore, a robust methodology for early checking of connection integrity at the RTL and netlist level is crucial. Current formal, simulation, and script-based approaches for connectivity checking face challenges, such as a lack of key functionality, scalability limitations, debugging difficulties, and inefficient usability.
In contrast, this paper introduces a novel static approach to defining a comprehensive set of rules at both the block and top-level, addressing issues such as the elimination of improper connectivity that may lead to block abutment issues during physical design, clock domain identification for specific instance ports, detection of driven pins within a module and ensuring glitch-free input pins for specified instances. We successfully verified connectivity and glitches on an active SoC design with this methodology in a matter of days, as opposed to weeks of work with alternative methods.
In contrast, this paper introduces a novel static approach to defining a comprehensive set of rules at both the block and top-level, addressing issues such as the elimination of improper connectivity that may lead to block abutment issues during physical design, clock domain identification for specific instance ports, detection of driven pins within a module and ensuring glitch-free input pins for specified instances. We successfully verified connectivity and glitches on an active SoC design with this methodology in a matter of days, as opposed to weeks of work with alternative methods.
Event Type
Engineering Track Poster
TimeTuesday, June 255:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP