Presentation
A Novel Automation flow to generate SV-UVM Testbench with integrated BFMs
DescriptionThe design verification (DV) phase in chip production lifecycle is a crucial and time-consuming process.
For any new IP/SoC, creating a DV environment from scratch is time consuming, repetitive and cumbersome task. This usually requires 2-3 weeks of effort from DV Engineer. Furthermore, if third party VIPs are required, it takes more time to figure out the configurations needed for the same and sometimes takes unnecessary debug sessions.
This paper presents a newly developed automation flow which takes inputs from the user on required BFMs (in house or third-party) and generates a testbench with all the UVM components in it. These include, the TB top, UVM-Env, UVM agents, scoreboard etc. The BFMs are picked from a common location which can be made accessible to all the DV work areas. The BFMs are instantiated here with known config sets and user need only give minimal information to the automation flow.
As of today, this flow has been implemented for IPDV. It can be extended to be used on SOC DV in future.
For any new IP/SoC, creating a DV environment from scratch is time consuming, repetitive and cumbersome task. This usually requires 2-3 weeks of effort from DV Engineer. Furthermore, if third party VIPs are required, it takes more time to figure out the configurations needed for the same and sometimes takes unnecessary debug sessions.
This paper presents a newly developed automation flow which takes inputs from the user on required BFMs (in house or third-party) and generates a testbench with all the UVM components in it. These include, the TB top, UVM-Env, UVM agents, scoreboard etc. The BFMs are picked from a common location which can be made accessible to all the DV work areas. The BFMs are instantiated here with known config sets and user need only give minimal information to the automation flow.
As of today, this flow has been implemented for IPDV. It can be extended to be used on SOC DV in future.
Event Type
Engineering Track Poster
TimeTuesday, June 255:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP