Presentation
Finding Bugs in RTL Descriptions: High-Level Synthesis to the Rescue
DescriptionMost RTL designs originate from behavioral descriptions specified in C or C++. These are often written by SW designers. Hardware (HW) designers then manually build an efficient hardware implementation of that application using a Hardware Description Language (HDL) like Verilog or VHDL. Although it has been shown that High-Level Synthesis (HLS) provides a direct path to synthesizing these behavioral descriptions into RTL, the quality of the generated RTL is often still unacceptable, hence, requiring the manual RTL design. This is nevertheless time consuming and error prone. In particular, finding bugs introduced in the manual design is very tedious as HW designers typically rely on long simulations that generate large waveforms that have to be thoroughly scrutinized.
To address this, in this work we present an automated method to accurately point to where in an RTL description a bug is located by using HLS. In particular we leverage the ability of HLS to generate a variety of different micro-architectures to automatically find a design architecturally `similar' to the manually optimized one in order to help locate the bug.
To address this, in this work we present an automated method to accurately point to where in an RTL description a bug is located by using HLS. In particular we leverage the ability of HLS to generate a variety of different micro-architectures to automatically find a design architecturally `similar' to the manually optimized one in order to help locate the bug.
Event Type
Research Manuscript
TimeTuesday, June 252:00pm - 2:15pm PDT
Location3010, 3rd Floor
EDA
RTL/Logic Level and High-level Synthesis