Presentation
Labidus: Productive Accelerator Development via Configurable Soft Processors
DescriptionDespite the attractive performance and power-efficiency of application-specific hardware accelerators using FPGAs, emerging applications are often slow to benefit from them due to the high development overhead caused by the steep learning curve of its tools and paradigms, especially for control-heavy with irregular computation patterns. We present Labidus, a conveniently programmable on-chip cluster of RISC-V soft processors, augmented with a pool of queue-semantic accelerator functions automatically configured for each user software via static analysis. We evaluate Labidus using four established scientific computing applications, and demonstrate it can compete with, and sometimes even outperform manually optimized hardware accelerators on GB-scale workloads
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security