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Presenter

Weihua Sheng
Huawei
Presentations
Research Manuscript
Size-Optimized Depth-Constrained Large Parallel Prefix Circuits
EDA
RTL/Logic Level and High-level Synthesis
Research Manuscript
GCS-Timer: GPU-Accelerated Current Source Model Based Static Timing Analysis
EDA
Timing and Power Analysis and Optimization
Work-in-Progress Poster
ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security