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Presenter

Zhiheng Yue
Tsinghua University
Presentations
Research Manuscript
Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization
Design
In-memory and Near-memory Computing Circuits
Research Manuscript
CAP: A General Purpose Computation-in-memory with Content Addressable Processing Paradigm
Design
In-memory and Near-memory Computing Circuits