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Presenter

Jungyun Choi
Samsung
Presentations
Engineering Track Poster
Unified Waveform Analysis Platform for Tr.-Level Design Verification
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Row-Based Placement and Legalization for Mixed Signal Power Delivery IP in Memory
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Methodology of linking the LDR and DRC code by automatically generated test pattern
Back-End Design
Embedded Systems
Front-End Design
IP
Back-End Design
Memory IO Block Routing Optimization using Semi-Automation of Single Trunk Steiner Tree Routing
Back-End Design
Design
Engineering Tracks