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Presenter

Hongce Zhang
The Hong Kong University of Science and Technology (Guangzhou)
Presentations
Research Manuscript
E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis
EDA
RTL/Logic Level and High-level Synthesis
Research Manuscript
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
EDA
Timing and Power Analysis and Optimization