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Presenter

Nanditha Rao
International Institute of Information Technology, Bangalore
Presentations
IP
Hybrid Tiled Vector Systolic Architecture to
Engineering Tracks
IP
Work-in-Progress Poster
Heterogeneous Vector Accelerator for Matrix Multiplications on FPGA
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Chair of Sessions
IP
Methodologies for Streamlining SoC Design Challenges
Engineering Tracks
IP