Session
Heterogeneous and Reconfigurable Architecture: Applications and Tools
Session Chairs
DescriptionHardware accelerators are integral in modern computing systems to deliver the required performance-per-Watt efficiency by exploiting fine-grained spatial concurrency. Programmable and reconfigurable accelerators are important in extending hardware acceleration efficiency to a still larger and more diverse share of computing tasks. This session showcases novel applications of Field Programmable Gate Arrays, GPUs, and chiplets to accelerate new computing problems. This session also presents new advances in EDA algorithms to improve application mapping to Coarse-Grained Reconfigurable Architectures. The final paper explores reconfiguration within a von Neumann processor datapath to efficiently specialize to changing applications.
Event TypeResearch Manuscript
TimeWednesday, June 263:30pm - 5:30pm PDT
Location3003, 3rd Floor
Design
SoC, Heterogeneous, and Reconfigurable Architectures
Presentations
3:30pm - 3:45pm PDT | CLUMAP: Clustered Mapper for CGRAs with Predication | |
3:45pm - 4:00pm PDT | PT-Map: Efficient Program Transformation Optimization for CGRA Mapping | |
4:00pm - 4:15pm PDT | G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner | |
4:15pm - 4:30pm PDT | SpectraFlux: Harnessing the Flow of Multi-FPGA in Mass Spectrometry Clustering | |
4:30pm - 4:45pm PDT | MSMAC: Accelerating Multi-Scalar Multiplication for Zero-Knowledge Proof | |
4:45pm - 5:00pm PDT | PHD: Parallel Huffman Decoder on FPGA for Extreme Performance and Energy Efficiency | |
5:00pm - 5:15pm PDT | Chiplever: Towards Effortless Extension of Chiplet-based System for FHE | |
5:15pm - 5:30pm PDT | Geneva: A Dynamic Confluence of Speculative Execution and In-Order Commitment Windows |