Session

DescriptionThis interdisciplinary session showcases advances in low-power, high-performance architecture and circuit design for AI/ML and imaging applications, and the use of AI/ML in analog and digital circuit design. It starts with a low-power architecture for high-resolution image sensing. The second paper optimizes memory, power, and security for hyperdimensional computing. The third paper improves performance prediction of circuit topologies within learning-based analog circuit optimization. The fourth paper introduces ChatCPU, an LLM-based hardware design and verification platform. The next two papers aim to accelerate model training and inference with reduced-circuit-size and low-power architecture designs. The seventh paper proposes a Generative AI and ML-based framework to drive automated analog layout synthesis. The session concludes with a hardware accelerator design to handle the unique computational requirements of neural volume rendering.