Session
Racing Against Time: Innovations in Timing
Session Chairs
DescriptionThis session showcases breakthroughs in timing, from timing prediction and analysis to its application. It begins with novel methods for timing prediction, moves through significant advancements in GPU-accelerated static timing analysis for rapid verification, introduces efficient techniques for critical path selection, and concludes with statistical modeling for yield estimation. This session encapsulates the forefront of timing, promising to elevate design accuracy and speed in the semiconductor industry.
Event TypeResearch Manuscript
TimeTuesday, June 2510:30am - 12:00pm PDT
Location3008, 3rd Floor
EDA
Timing and Power Analysis and Optimization
Presentations
| 10:30am - 10:45am PDT | Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization | |
| 10:45am - 11:00am PDT | Disentangle, Align and Generalize: Learning A Timing Predictor from Different Technology Nodes | |
| 11:00am - 11:15am PDT | GCS-Timer: GPU-Accelerated Current Source Model Based Static Timing Analysis | |
| 11:15am - 11:30am PDT | G-PASTA: GPU Accelerated Partitioning Algorithm for Static Timing Analysis | |
| 11:30am - 11:45am PDT | Ink: Efficient Incremental k-Critical Path Generation | |
| 11:45am - 12:00pm PDT | LVF2: A Statistical Timing Model based on Gaussian Mixture for Yield Estimation and Speed Binning |