Session
Analog Design Verification and Layout Synthesis Rethought
DescriptionThis session solves core EDA problems for analog circuit design. The first five papers improve verification starting with advanced simulation methods for complex (extracted) circuits: simulations are empowered by a memory-efficient solution for sparse matrices and a powerful graph sparsification algorithm; an efficient capacitance approximation methodology is proposed to enhance parasitic extraction while PCB-S-parameters are modeled by an AI-driven estimator; and a gradient descent approach improves equivalence checking. Finally, an AI approach tackles the analog layout synthesis problem with 3DGNNs.
Event TypeResearch Manuscript
TimeWednesday, June 2610:30am - 12:00pm PDT
Location3010, 3rd Floor
EDA
Analog CAD, Simulation, Verification and Test
Presentations