Session
Explore Concepts of STA Thru Insightful Craftsmanship
Session Chair
DescriptionExplore how you drive STA through 3D to ML techniques or simply closing timing on large designs be it through pruning margins, multiple clock sources or just partitioning effectively.
Event TypeBack-End Design
TimeMonday, June 2410:30am - 12:00pm PDT
Location2008, 2nd Floor
Back-End Design
Design
Engineering Tracks
Presentations
| 10:30am - 10:45am PDT | TSV KOZ separation 3DIC P&R area optimization methodology considering device impact by TSV | |
| 10:45am - 11:00am PDT | ML based PPA Push using DRV Prediction | |
| 11:00am - 11:15am PDT | Model Margining Algorithm for High Performance SOC closure | |
| 11:15am - 11:30am PDT | Pruning Netlist: A Smarter Approach to Efficient and Reliable Circuit Characterization | |
| 11:30am - 11:45am PDT | Clock parameter tuning with an intelligent adaptive learning to improve performance and power of Multisource Clock Tree Synthesis | |
| 11:45am - 12:00pm PDT | An effective Hierarchical STA solution for closing Large SoC Design |