Session
Electron Signatures for Predicting the Diagnosis!
Session Chair
DescriptionEnhance your work to identify the signatures underlying high bandwidth interfaces, chip package board co-design or just closing optical and silicon robustness from leaking secrets to the outside world.
Event TypeBack-End Design
TimeWednesday, June 2610:30am - 12:00pm PDT
Location2008, 2nd Floor
Back-End Design
Design
Engineering Tracks
Presentations
| 10:30am - 10:48am PDT | UCIe-A 32GT/s power distributed network design-optimization at organic interposer with localized integrated passive decoupling capacitors Presenter | |
| 10:48am - 11:06am PDT | Die, Package and PCB Co-design for Low Area, High Signal to Power Pin Ratio in High Frequency SOC designs | |
| 11:06am - 11:24am PDT | Si Backside Side-Channel Leakage and Simulation of Cryptographic IC Chips | |
| 11:24am - 11:42am PDT | System Aware IO Integrity Signoff | |
| 11:42am - 12:00pm PDT | Pre-Silicon Photon Emission Modeling and Optical Side-Channel Simulation |