Session
Methodologies for Streamlining SoC Design Challenges
DescriptionSoC design poses several challenges in terms of design flow and methodologies. The use of advanced and automated methods is crucial, especially for compute-intensive workloads. This session presents various topics on design methodologies such as: accelerating placement-aware timing closure for NOCs, an open-source design flow promising support for generative AI, accelerating DRC checks, CDC multimode signoff methodology, droop mitigation and scalable sign-off/QA flow.
Event TypeIP
TimeTuesday, June 2510:30am - 12:00pm PDT
Location2010, 2nd Floor
Engineering Tracks
IP
Presentations
10:30am - 10:45am PDT | Advancing Power Signoff for High Speed ΔΣADC Organizer | |
10:45am - 11:00am PDT | Considering Selective Resistance Extraction for Performance & Accuracy Trade-off for Memory IP Simulation | |
11:00am - 11:15am PDT | Fast and Deterministic Memory Yield Estimation Using Machine Learning Augmented Statistical Simulations | |
11:15am - 11:30am PDT | Low-Cost Built In Self Test IP for Nextgen Continuous Time Sigma Delta ADCs | |
11:30am - 11:45am PDT | An All-Digital Transient Filter IP for Serial Links | |
11:45am - 12:00pm PDT | Interfacing High-Voltages Directly to Low Power CMOS Process Die for RF, MEMs and Analog Applications |