Session Full Program · Contributors · Organizations · Search Program · Flagged · Happening NowMore…Search ProgramFlaggedHappening NowEngineering Track Poster: Monday Engineering Track Poster ReceptionEvent TypeEngineering Track PosterTimeMonday, June 245:00pm - 6:00pm PDTLocationLevel 2 Exhibit HallTopicsBack-End DesignEmbedded SystemsFront-End DesignIPPresentationsDie-Level Dynamic-IR Analysis Shift-Left Enabled by RedHawk-SC SigmaDVDAuthorsRuiqi WuRan ZhangLuca CuiChang ZhaoMarc ZhengModeling Optimal Number of Tap-points for Flexible H-tree During Clock Tree SynthesisAuthorsAnup kumarAkshay MankotiaDeveloping Software Test Library (STL) as a Safety Mechanism for Vision AI DSPAuthorsNoam MeserZvika MelamedSesha Sai Kumar C VAyman MouallemFares JaraisyAchieving High Local Noise Coverage in Dynamic EMIR Analysis using SigmaDVDAuthorsGovind PalAmit JangraKoshy JohnReducing Interlayer misalignment caused by BLE (Bulk Layout Effect) : Solutions for improving in-chip uniformity of alignment between two layersAuthorsHyejin KimOhhun KwonJichang SimDaehee LeeHyunmi JiJooseong LeeFaster Timing Closure of Multiple Power Domains Based Designs with SMVAAuthorsRajnish GARGRohit GoelA Single Source Unified Approach to CSR Register DevelopmentAuthorsInsaf MelianeAndy NightingaleRich WeberSystematic Flow on AC Scan Timing/ATPG Constraint GenerationAuthorsChen Yuan KaoYi Hsuan ChiuQuality Assurance of DRC deck for Devices by SKILL AutomationAuthorsAmbika BhardwajChirag AgarwalPiyush Sonikancou traoreA Novel Methodology for Library Characterization and Modeling Considering Local Layout EffectAuthorsYoobeom KimHyunseung SeoCheolJun BaeJingon LeeChul RimEdson GomersallRamesh KamathShupeng CuiMehar GuptaEarly Clock Tree Power Estimation and Correlation at SoC: A Case StudyAuthorsSri Sai Pavan PasumarthiSudheer YadapalliVineet OoramkumarathDesign Enablement of 2D/3D Power-Thermal Self-Consistent AnalysisAuthorsMohamed NaeimYun DaiDwaipayan BiswasDragomir MilojevicA Novel Approach to Cost-Efficient Hybrid Cloud Solutions with SeaScape's Data Lake and Micro-ResiliencyAuthorsMohit SrivastavaAjay ChopraNaveen BSankar RamachandranSooraj JPVyom GargSystematic Verification Framework for Memory Subsystem Ensuring Reliability and RobustnessAuthorsVatsal PatelPooja PatelDharini SubashChandranRitesh DesaiPratibha SukhijaPratibha SukhijaAccelerate RF Board BOM Simulation with ADS Design AutomationAuthorsZhen ZHANGTom DemuerJuneyi PENGShengkang ZHANGA "Shift-Left" Analysis Flow For Layout Parasitics Of High Speed Analog Mixed Signal DesignAuthorswei weiYaping HuangJie HuXiaomei YouWei WeiSmart Testing: Integrating Fault Simulation and AI/ML for Efficient IP ValidationAuthorsHimanshu VishwakarmaPriyanka GharatGopi Srinivas DeepalaTiming Closure Methods on 5nm Design ChallengesAuthorPatricia FongRedefining Hierarchical Power Integrity signoff for Ultra-Large System-on-ChipsAuthorsPiyush JainRossana LiuHailang WangApurva SoniMedha KulkarniPranav RanganathanChidambaram RakkappanAmit JangraGodwin RajasekharSreekanth RajanEfficient HBM Channel Design in 2.5D Silicon Interposer with Signal Integrity OptimizationAuthorsFeng LingYan MaMicrosoft's Comprehensive IP Handoff FlowAuthorsMartin SanchezSiddharth RavikumarMary RayburnCOBRA : Code Coverage Measurement Technique for ARM-based firmware using Binary Modification TechnologyAuthorwonchol kim3DIC prototype design and transient early thermal analysisAuthorsYongjin HongKiwook JungKi-Ok KimByunghyun LeeSangyun KimAn Integrated Behavioral Modeling Method for Mixed Signal IPsAuthorsBhupendra SinghRahul KumarPallav KumarJean-Aranud FrancoisMitu MittalAnil DwivediEnhanced State-Propagation based Vectorless IR-Drop Analysis Emulating Realistic Silicon BehaviorAuthorsSubhadeep GhoshRishabh SinghRuchin GuptaSushant SharmaGaurav VarshneyMethodology to analyze and optimize SOC performance and cost using function agnostic cycle accurate modelsAuthorsAtul LeleAnuvrat SrivastavaAjeet SinghAshutosh MishraAn Effective Method of Evaluating Chip Power Noise in System-level with iCPMAuthorsChenxi YangYongsheng GuoPing DingLi ZouFeng WuJiangtao Zhangjianguo zhangKeqing OuyangCDC Simulation Checker Implementation for Constant and Quasi-static Data PathsAuthorYoungchan LeeAdvancing Low Power Design in the Era of Rising Energy Footprints: Insights from IEEE 2416 Standard and Future ExtensionsAuthorsNagu DhanwadaJerry FrenkilW. Rhett DavisDaniel CrossAkil SuttonAli SadighLeigh-Anne ClevengerNovel Way of Checking and Analyzing Peak to Peak Voltage Variation Challenges for High Computational Multiprocessors SOCAuthorsAmit SinghGovind PalAnil YadavAmit JangraKoshy JohnAccelerating Automated Custom Layout Creation Through Smart Design Intent MigrationAuthorsGirish VaidyanathanSravasti NairA Decade of Evolution in Formal VerificationAuthorsErik SeligmanM V Kiran KumarElectromagnetic Solutions From Design to Sign-Off Stage For High-Speed SerDes DesignAuthorsYuhang ZhaoJinRong YanHang SunXuewei DingXiaomei YouRodger LuoYuhang ZhaoRapid Retargeting of Formal Connectivity Verification of AI FPGA SystemsAuthorsLinh NguyenBenjamin TingNguyen LeJin HouRahul SethSasa StamenkovicCharting Uncharted Waters: Functional Simulation Reshaping CDC/RDC Constraints SignoffAuthorssuhas SDeepmala SachanPonsankar ArumugamRitesh JainHolistic Approach on 3DIC PlanningAuthorsVenkata ChinniSRUTI L SHRIDHARTadasa MahapatraSandeep JadhavDesign Automation of Minimal Layer Count Microprocessor 2.5D Silicon InterposerAuthorsOmer VikinskiBasil TarabieaAlexander WaizmanDesign Closure Methodology using stage wise checkers by Ease of Review to minimize Physical Design Implementation & Closure TATAuthorsShilpi SrivastavaDaniel HandJagadeesh GnanasekaranAreal and Time Decomposed Phalanx based Dynamic IR-Drop Prediction using DNN(Deep Neural Network) at Earlier stage of Design cycleAuthorsSeihyung JangGyusun ParkKibum KangYun RaKisun KimKisik LeeChangsik LeeHongsok ChoiTaejin KimHongpa CheDongchul KangA Closed Loop IR and Timing Comprehensive Co-Signoff MethodologyAuthorsOnkar HuleRossana LiuMedha KulkarniHailang WangAmit GargPranav RanganathanSreekanth RajanAmit JangraOvercoming the Growing Challenge of IR Drop by Effective Power Grid Enhancement during Chip FinishingAuthorsRahul Sai T GovindaswamySmitha Shivaji KamathiBen AllenRavikanth KosuruPrateek PendyalaZvart AskanazyanChristian MilesHeba SharafEsraa SwilliamJeff WilsonGurpreet Lamba2.5D Design Breakthrough: Unleashing the Power of Automated EMIB Bridges.AuthorSam MirzaGlobalized bulk biasing based substrate noise reducing method for size reduction in digital circuitAuthorsChangyeon YuAhreum KimPansuk KwakDongku KangAdvanced LLE aware Timing Signoff MethodologyAuthorsYoobeom KimJingon LeeChul RimHyunseung SeoSangwoo HanAhmed ShebaitaTajendra SinghLi DingSunik HeoMachine-Learning-Driven Floorplan-Aware Power Delivery Network Co-PlanningAuthorsBogdan TabacaruJerome ToublancAI-Assisted Design Optimization for Extensive Design Spaces: Handling 260,000+ CombinationsAuthorsAustin RhodesMohamed AtouaExecutable Tables, 'A Journey from Document to Simulation Capable, Exemplified Using DDR5 'AuthorsRahil JhaJoseph BauerRahil JhaPredicting Computer Resource Needs using Machine Learning and Conventional DesignAuthorJustin ConklinCalibre Autowaiver for Early DRC & DFM Analysis In Big Die DesignsAuthorsVenkata ChinniRahul AgarwalSRUTI L SHRIDHARForward Progress Testing: Saftey vs Liveness AssertionAuthorAnkit Kumar GargProgrammable IO Ring Builder and checkerAuthorsManoj KumarAnurag MittalPraveen JakkiAvinash GuptaPriyanshi JainPriyanka GoelShift-left Solution for Enhancing Power Integrity in physical design construction with RedHawk-FusionAuthorsKiran AdhikariHailang WangKarthikk SridharanRossana LiuJin WangSreekanth RGodwin RajasekharNoise Fixup: Finding and Fixing Noise Problems ( Chop and Swap )AuthorAdam MathenyPnr implementation challenges in 3d icAuthorsArvind Kumar Mishrachoudhary Aditya KumarJeshwanth RahulSandeep JadhavSigmaDVD: High Coverage Solution for Power Integrity SignoffAuthorsAnusha VemuriEmmanuel ChaoSantosh SantoshChidambaram RakkappanEd DeetersLeveraging several automated techniques and methodologies for faster coverage closure and design sign-offAuthorsGulshan SharmaSougata BhattacharjeeThe Designer's Superpower! Early Circuit Verification with Calibre nmLVS ReconAuthorsKesmat ShahinRahul Sai T GovindaswamySmitha Shivaji KamathiAnish PadhiRakesh ReddyKarishma QureshiRajashekar SuraGurpreet Singh LambaA Novel approach to implement FuSA Feature in Complex Automotive SoCs Using USFAuthorsDEEPTI KHURANAManikanta AkulaMemory Clusters – Divide the design and optimize MBIST insertion effortsAuthorsSanthosh RamappaSubhash BaraiyaMethodology of linking the LDR and DRC code by automatically generated test patternAuthorsDongjin KimKwonjae KimSeyeon MoonBoyoung LeeYoungwook KimJungyun ChoiOn Cloud Secured Collaboration From chips to embedded systemsAuthorsSmriti JoshiManuel ReiAutomated Place and Route based solution for Custom BlocksAuthorsRajeev SinghAtul BhargavaAkshita BansalVishesh KumarVijay Singh KhatiA Novel methodology for re-simulation of block vectors helping validate Power Optimization QoR 20x fasterAuthorsBhupesh PrajapatParul DoharePratik TalekarManish KumarDivya PariharSachin KumarMahima JainMohammed FahadBalancing Power and Performance: The Hybrid Clock Network Approach for Network on chipsAuthorsPallapu Lakshmi SarvaaniSubba AnnapalliPonnada Appala NaiduShift-left methodology to identify invalid voltage level shifts & validate signal pins' P/G association in IPs/Block's UPF & .LIB views using PERC's static-voltage tracing mechanismAuthorsSarvagya TiwariGAZAL SINGLAShubham SachdevaEmpowering Early-Stage Design: An Automated Solution for Die Size Estimation and IO Ring CreationAuthorsGaurav VarshneyDheeraj HAMegha NaikMuraliMohan ThotaAutomated Floorplan Scaling Solutions and FrameworkAuthorsSivaramakrishnan Harihara SubramanianVenkatesh RSKhris Valencia ChaconBus Delay Skew Minimization for High Bandwidth Memory DesignsAuthorsKwangok JeongSeoklip KiSua KimAlpesh KothariJaejun LeeJeongGuk ChoiRaghu GudeSung-Soon ChoiStruct Based Lower Level Modelling Using SystemVerilog UDT for Verification of Power Management ICAuthorsVijay KumarKeerthana KCeleste Anil LagaliMemory Interface Architectures for Test Time Reduction in Zero DPPM SoCsAuthorsNitesh MishraHrithik SahniOvercoming Collaboration Hurdles in High-Tech Product Development with Keysight tool on Azure infrastructure.AuthorsAmit VardeJoe TostenrudeUnified Waveform Analysis Platform for Tr.-Level Design VerificationAuthorsChoi WonwooKwangsun KimSungho ParkHyungjung SeoYounsik ParkJungyun ChoiSolving Memory Subsystem Verification Challenges for Multi-Instance DesignsAuthorsShyam SharmaManish Chand
