Session Full Program · Contributors · Organizations · Search Program · Flagged · Happening NowMore…Search ProgramFlaggedHappening NowEngineering Track Poster: Tuesday Engineering Track Poster ReceptionEvent TypeEngineering Track PosterTimeTuesday, June 255:00pm - 6:00pm PDTLocationLevel 2 Exhibit HallTopicsBack-End DesignEmbedded SystemsFront-End DesignIPPresentationsDashboard Model for Foundry Early Node Assessments using Synopsys Design.daAuthorsLuna KangJayson SeoAnn-Woo LeeJames BanPowerdash: A Comprehensive Framework for SOC Power Analysis and TrackingAuthorsVivek JoshiAtman KarEarly Validation of Random TB using Formal TechnologyAuthorEuibong JungLINKED LIST PROOF ACCELERATORAuthorArjun KumarEmpowering CDC analysis methodology with root cause analysisAuthorsAbdul MoyeenManish BhatiAsk-EDA: A conversational agent for tools, methodology, technology and design problemsAuthorsMichael KazdaBradley SearsNicholas ShropshireLuyao ShiAI-Enhanced Automated Optimization Workflow for HBM Interconnect on InterposerAuthorsShineng MaHao HuBin YuKeqing OuyangRodger LuoA PVT-robust Design with Electronic/Photonic Co-simulation Engine for Microring-based DWDM 3-D Silicon PhotonicsAuthorsChaerin HongLuca RaminiMarco FiorentinoAhsan AlamZeqin LuRaymond BeausoleilArchitecture Area Evaluation ToolAuthorsAshishkumar PalAdarsh TRKavithaa RajagopalanAccelerating IO Liberty Generation through ML based SolutionAuthorsPawan VermaAnil-kumar DwivediSaurabh SrivastavaAjay KumarWei-Lii TanSafeguarding datapath security requirements through formal verificationAuthorsNicolae TusinschiKeerthi DevarajegowdaSolving the antenna debug challenge in physical design verificationAuthorsRahul Sai T GovindaswamyNermeen HossamAnish PadhiKarishma QureshiGurpreet LambaRakesh reddy KatukuriResolving the seed promotion due to device layers derivationAuthorsPrachi MrudulaAtul BhargavaGAZAL SINGLACritical corners selection for standard cells LVF characterization using AIAuthorsAravind Radhakrishnan NairAjay KumarLars KishchukSSN and EMA Bus Path AutomationAuthorsGreg FordTrinath HarikrishnaGPU Accelerated Harmonic Balance SPICE SimulationAuthorsQikun XueChen ZhaoA Solution for Optimizing Customerized-MMBAuthorsFeilong PanMinqiang PengKeqing OuyangGuohua ZhouFengfeng TangDesign Methodologies for Minimizing Local Routing Congestions in Low-level Metal LayersAuthorsDaeyeon KimHONGSEOK CHOIMinkook KimSangyun KimA New Approach to Efficient Prelim Package Generation for Faster SOC ImplementationAuthorsBhupendra SinghShoikat DasSaurabh SrivastavaAnil DwivediFuture Proofing Chiplet Testbenches: Resilience in Multiprotocol EraAuthorsKilaru VamsikrishnaAnunay BajajShaikh SalehabibiKilaru VamsikrishnaFormal Tool Kit – A quick setup solution for formal analysisAuthorsPhanindra RamanujapuramRathnakar Madhukar YerraguntlaA Novel Flow to Verify SoC Integration with Formal Property VerificationAuthorsDavid VincenzoniMarcello DusiniDVD-aware STA and its silicon correlation results on 10nm test chipAuthorsJongyoon JungHyun-seung SeoByunghyun LeeRajat KukrejaAjay SahooJi-Hun KimDae-Hun JungAniket DeshmukhA Heuristic-Based Routing Methodology for Block-Level Memory Layout Routability EnhancementAuthorsSichan KimSeunghwan LeeAn Efficient Early Thermal Management Solution in 3DIC designAuthorsPing DingGuohua ZhouKeqing OuyangLi ZouShuqiang ZhangAn effective Hierarchical Top Scope Signal EM Flow for closing Large SOC DesignsAuthorsAdish MehtaRakesh ReddyUmberto GarofanoRatnakar BhatnagarSteve HarveyTowards a memory-address translation representation schemeAuthorRathnakar Madhukar YerraguntlaEarly detection of low power related issues using formal verificationAuthorsAndrea LopintoPaola BaldrighiMODEL BASED SYSTEM SEMICONDUCTOR ENGINEERINGAuthorsSmriti JoshiRosa GragossianTiming Takedown Reports 3AuthorLukas PetterssonPhysical Design With IntelligenceAuthorsBindu RaoJagadeesh GnanasekaranPrasenjit RaySai PrashantAnand KumaraswamySrinivas JammulaRaj DuaSimulation and Measurement of MOMCAP Breakdown Risk Based on TCADAuthorsKun ZhouJian WangTingting HunGuohua ZhouKeqing OuyangNavigating Instruction Length Decode: TAP into IP using three pronged FV TridentAuthorsVedprakash MishraAarti GuptaChallenges Faced in Formal Based MSI: Tackle Formal Problem with a Formal SolutionAuthorsAbhinav ParasharAyush JodhParthasarathy RameshHarish MaruthiyodanAbhinav ParasharGaurav VarshneyAutonomous Power Sequence validation solution for I/O using Solido Design EnvironmentAuthorsravinder kumarFouad MkalechEric MammiVani PriyaDIGITAL CONTINUITY FROM SEMICONDUCTOR EBOM TO MBOM AND BILL OF PROCESSAuthorsSmriti JoshiManuel ReiAdvancements in Source Synchronous Design Implementation: An EDA PerspectiveAuthorsKeshavkumar DurgakeriSubba Ramkumar Reddy AnnapalliPonnada NaiduNovel Preprocessing Technique for Data Embedding in Engineering Code Generation Using Large Language ModelsAuthorsYu-Chen LinAkhilesh KumarNorman ChangWen-liang ZhangMuhammad ZakirJyh-Shing JangRDL and Bump Automation for Early EMIR Analysis In 2.5D, 3D and Single DIE Designs using RedHawk-SC Design ECO'sAuthorsArpan BhowmikRaja Rama Chandra RaoRishikanth MekalaGoda Ananth SomayajiScalable modeling of dynamic voltage compression on timingAuthorTim HelveyMatched Placement and Routing using Synchronized Unit Cell ArrayAuthorsPriyanka MadaanAkshita BansalAshwani sanwalAvinash TripathiA module based automation for AXI performance monitoring, performance extraction and protocol checking.AuthorsNaveen SrivastavaAmresh LenkaSekhar DangudubiyyamMachine Learning-based feasibility estimation of digital blocks for improved productivity in Analog-on-Top Back-End design flowsAuthorsGabriele FaraoneEugenio SerianniDario LicastroNicola DiCaroloMichelangelo GrossoGiovanna FranchinoFlash-based storage systems exploiting the data period for performance and security enhancementAuthorsJung-Hoon KimSuhwan KimDaeun OhChallenges and Improvements in StandardCell OpenAccess Content for Analog DesignAuthorsAnuradha RayFrederic AvellanedaStephan WeberAnuradha RayAshish KumarAn Automated Solution for Streamlining Qualifications of Connectivity and DRC Across Diverse 3DIC Packaging TechnologiesAuthorsTaehyung LeeWoonggyu LeeMinkyung KimJihoon ParkHyojin KimChangyoon ShinJiseon LeeYoojeong YangSeungjae JungJongkoo kangAhmed SalehWatsonX and DDB for AI Based Design Analytics and VisualizationAuthorsKerim KalafalaNathaniel HieterDouglas KellerImplementing World's First Fully Integrated SoC Solution For Direct-To-Satellite IoT ConnectivityAuthorsSushanta SarmahAlpesh KothariRaghu Ram GudeAuto Grouping And Improvement Of IR Critical Regions Using Unsupervised LearningAuthorsArpan BhowmikAbhishek Mahesh ChinchaniRishikanth MekalaGoda Ananth SomayajiAccelerated Design Rule Learning for Silicon PhotonicsAuthorsApoorva VakilRomain FeuilletteTimothy MillerAn efficient QA methodology for SRAM librariesAuthorsHiroaki KoizumiShuji KatayamaSiddharth RavikumarMary RayburnA Data-Driven Automation Method of Liberty Model Characterization for Custom CellsAuthorsDongsub YoonYoungjin JuHyojin ChoiEnhancing and accelerating Verification with ad-hoc Python scriptingAuthorsEdoardo BolleaDavide SanalitroPlug-n-Play Testbench environment for ARM Coresight SoC-400AuthorsSowmya V MDhaval PanchalLalithraj MailappaSubramanian RNaveen SrivastavaSekhar DangudubiyyamElevating BFM Capabilities: seamless generation and validation of Proprietary Ethernet Frame in the absence of Physical interface connections with RTLAuthorsKrunal PatelShubham AgarwalKrunal PatelPeak Power Optimization using Active Datapath Operator ProfilingAuthorsVijay TayalSanchita GuptaAmit DeyAnil MishraHicham AnbarMohammad Saif AnsariManish KumarRisk Management in Volume DiagnosticsAuthorsPitchumani GuruswamyVishnu RajVirtual Instrumentation Based Predictive Checks for Shift-Left Low Power VerificationAuthorsSachin BansalYi LiuVijay PoosaM.Vaishnavi ReddyNupur GuptaVishal KeswaniAmit GoldieManish GoelIntegrated Calculation of Capacitances for Image Sensor Arrays and other Periodic DesignsAuthorsValery AxelradOgnjen MilicHigh Coverage QA for Process Variability Compensation in LVS Rule DeckAuthorsHeejae LimJaeyoung SoMinho JungJimin YeoYunseong LEEBonhyuck KooYongseok LeeAhmed SalehMohamed AlimamAvoiding CDC bugs introduced during Synthesis Optimizations and Netlist TransformationsAuthorssuresh barlaPARAS MAL JAINharish Aepalaanshul bansalGunjan MamaniaKenneth TrejosAnalysis of Rare Failure Events: An Improved Scaled-Sigma Sampling MethodAuthorNing LuMachine Learning Optimization Switch cells.AuthorSungsu ByunAn uptick on Automotive Safety Solutions using Cadence Implementation ToolsAuthorsJitendra JainAshwin RamamurthyHeterogeneous 3DIC Multi Voltage Timing SignoffAuthorsTusharkant MishraRanjith V RDamodaran TrikkadeeriSantosh VaranasiNew SoC Creation Flow based on Extraction and recreating from previous SoCAuthorsMaël RabéChouki AktoufRow-Based Placement and Legalization for Mixed Signal Power Delivery IP in MemoryAuthorsJeongyoon LeeKyeongrok JoSeunghwan LeeSeungkwang HongHeejin BaeJiwon WooYoungwook KimJungyun ChoiNext-Gen comprehensive IR analysis with Ansys SigmaAVAuthorsPranav RanganathanMedha KulkarniChip StratakosVeshal SridharMallik VusirikalaTapeout Data Preservation and automatic archival tagging for Optimal Disk Space ManagementAuthorYamini RavishankarA Novel Automation flow to generate SV-UVM Testbench with integrated BFMsPresentersParthasarathy RameshSagar JogurRaminder KaurAtul LeleCoverage-based FV signoff – The complete cleanup methodologyAuthorsGilboa AlinDaher KaissAnmol PatelAarti GuptaGavriel GavrielovDevelopment of SystemC-based Security VP for In-House SED SSD Firmware Verification and Application of libFuzzerPresenterCHANGWON KIMTrue-Hybrid SaaS Cloud Architectures for EDA WorkloadsAuthorsRavi PoddarAmit VardeNupur BhongeAutomated Constraint Promotion Methodology from IP to SoC for Complex DesignsAuthorsMallik DevulapalliRimpy ChughAdvanced Static Methodology for Complete Connectivity and Glitch SignoffAuthorsAbhishek GhateSaurav ChoudharyVikas SachdevaEnhancing Analog Mixed-Signal (AMS) Verification: Advanced Methods for Runtime and Scope OptimizationAuthorsAadhar SharmaAvinash ChaudharySooraj SekharLakshmanan BalasubramanianGaurav Varshney
