Session Full Program · Contributors · Organizations · Search Program · Flagged · Happening NowMore…Search ProgramFlaggedHappening NowWork-in-Progress Poster: Tuesday Work-in-Progress PostersEvent TypeWork-in-Progress PosterTimeTuesday, June 256:00pm - 7:00pm PDTLocationLevel 2 LobbyTopicsAIAutonomous SystemsCloudDesignEDAEmbedded SystemsIPSecurityPresentationsA General Purpose IMC Architecture with ADC-Awared Neural NetworksAuthorsMin-Gwon SongShin-Uk KangMin-Seong ChooA Hardware-Aware Framework for Practical Quantum Circuit KnittingAuthorsXiangyu RenMengyu ZhangShengyu ZhangYicong ZhengAntonio BarbalaceA Hierarchical Dataflow-Driven Heterogeneous Architecture for Wireless Baseband ProcessingAuthorsLimin JiangYi ShiHaiqin HuQingyu DengSiyi XuYintao LiuFeng YuanSi WangYihao ShenFangfang YeShan CaoZhiyuan JiangA High-Throughput, Energy-Efficient, and Constant-Time In-SRAM AES Engine with Massively-Parallel Bit-Serial ExecutionAuthorsAndrew DervayWenfeng ZhaoA novel method to analysis the wafer defect patterns using an image matching algorithm based on deep neural networksAuthorsYoungwook KwonSumin OhHyunJin KimA Parallel-trial Double-update Annealing Algorithm for Enabling Highly-effective State Transition on Annealing ProcessorsAuthorsAkira HyodoSatoru JimboDaiki OkonogiGenta InoueThiem ChuMasato MotomuraKazushi KawamuraA Quantum Solver for the Boolean Matching ProblemAuthorsMarco VenereAlessandro BarenghiGerardo PelosiA Synthesis Methodology for Intelligent Memory Interfaces in Accelerator SystemsAuthorsAnkur LimayeNicolas Bohm AgostiniClaudio BaroneVito Giovanni CastellanaMichele FioritoFabrizio FerrandiAndres MarquezAntonino TumeoAdaptive Neurosurgeon: DNN Computing Latency Minimization for Mobile Edge IntelligenceAuthorsGang WuQianru WangBiao HuAdditive Partial Sum QuantizationAuthorsPingcheng DongYonghao TanDong ZhangYongkun WuXijie HuangShi-Yang LiuYu LiuXuejiao LiuPeng LuoLuhong LiangFengwei AnKwang-Ting ChengAddressing the Diversity in AI Computing: An On-chip Programmable AcceleratorAuthorsGopikrishnan Raveendran NairFengyang JiangJeff ZhangJae-sun SeoYu CaoAiDAC: A Low-Cost In-Memory Computing Architecture with All-Analog Multibit Compute and InterconnectAuthorsZihao XuanSong ChenKang YiAMARETTO: Enabling Efficient Quantum Algorithm Emulation on Low-Tier FPGAsAuthorsChristian ContiDeborah VolpeMariagrazia GrazianoMaurizio ZamboniGiovanna TurvaniAn Analytical Fidelity Model for Readout Circuitry with Multiple Co-Existing Non-Idealities for Superconducting Quantum ComputingAuthorsYao TongQuan ChenAn Application of Information Flow Tracking to Hardware Trojan DetectionAuthorsRyoichi IsawaNobuyuki KanayaDaisuke InoueAn Effective Timing Driven Placement with Accurate Differentiable Timing Approximation IntegrationAuthorsXu HeRenjun ZhaoChenjing YangYushan WangYao WangPeiyu LiaoYibo LinBei YuAnalytical Modeling and Electro-Thermal Benchmarking of 2.5D/3D Heterogeneous Integration for AI ComputingAuthorsZhenyu WangJingbo SunA. Alper GoksoySumit MandalJae-sun SeoVidya A. ChhabriaJeff ZhangChaitali ChakrabartiUmit OgrasYu CaoApprox-T: Design Methodology for Approximate Multiplication Units via Taylor-expansionAuthorsShang-shang YAOQing-jie LANGLi ShenKai LUArchitectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)AuthorsDhandeep ChallagundlaIgnatius BezzamRiadul IslamAre Adversarial Examples Suitable To Be Test Suites for Testing Deep Neural NetworksAuthorWei KongAthena: Add More Intelligence to RMT-based Network Data Plane with Low-bit QuantizationAuthorsYunkun LiaoHanyue LinJingya WuWenyan LuXiaowei LiGuihai YanAutoFlow: Inferring Message Flows From System Communication TracesAuthorsBardia NadimiHao ZhengB-Ring:An Efficient Interleaved Bidirectional Ring All-reduce Algorithm for Gradient SynchronizationAuthorsRuixing ZongJiapeng ZhangGuoqing XiaoZhuo TangKenli LiBalancing and Minimizing Energy Consumption of Federated Learning in Heterogeneous Mobile Edge IoTAuthorsZehao JuTongquan WeiBayesian learning-driven Memory Design Exploration with Automated Circuit Variant GenerationAuthorsDongho KimSeokhun KimJunseo LeeHongwon KimSangheon LeeJihwan ParkHanwool JeongCDA: Collaborative Computing Using Centralized-Distributed Architecture for Smart SensingAuthorsErxiang RenCheng QuLi LuoYonghua LiZheyu LiuXinghua YangQi WeiFei QiaoCellRejuvo: Rescuing the Aging of 3D NAND Flash Cells with Dense-Sparse Cell ReprogrammingAuthorsHan-Yu LiaoYi-Shen ChenJen-Wei HsiehYuan-Hao ChangHung-Pin ChenCooling the Chaos: Mitigating the Effect of Threshold Voltage Variation in Cryogenic CMOS MemoriesAuthorsRakshith SaligramAmol GaidhaneSuman DattaYu CaoArijit RaychowdhuryDeputy NoC: A Case of Low Cost Network-on-Chip for Neural Network Accelerations on GPUsAuthorsKhoa HoSiamak BiglariJustin GarrigusHui ZhaoEfficient Synaptic Delay Acceleration in Digital Event-Driven Neuromorphic ProcessorsAuthorsRoy MeijerPaul DettererAmirreza YousefzadehAlberto Patiño-SaucedoGuangzhi TangKanishkan VadivelYingfu XuMario KonijnenburgManil Dev GomonyFederico CorradiManolis SifalakisELF: Efficient Logic Synthesis by Pruning Redundancy in RefactoringAuthorsDimitrios TsarasLei ChenXing LiWeihua ShengZhiyao XieMingxuan YuanEnabling Fast 2-bit LLM on GPUs: Memory Alignment, Sparse Outlier, and Asynchronous DequantizationAuthorsJinhao LiShiyao LiJiaming XuShan HuangJun LiuYaoxiu LianYu WangGuohao DaiEnhancing Performance of Deep Neural Networks with a Reduced Retention-Time MRAM-Based Memory ArchitectureAuthorsMunhyung LeeTaehan LeeJunwon YeoHyukjun LeeEscaping local optima in global placementAuthorsKe XueXi LinYunqi ShiShixiong KaiSiyuan XuChao QianESFA: An Efficient Scalable FFT Accelerator Design Framework on Versal AI EngineAuthorsHao YangLinfeng DuWei ZhangExploring Distributed Circuit Design Using Single-Step Reinforcement LearningAuthorsJiayu LiMasood MortazaviNing YanAlgorithm-Hardware Co-Design of Distribution-Aware Logarithmic-Posit Encodings for Efficient DNN InferenceAuthorsHesham MostafaAdam GrabowskiMd Asadullah TurjaJuan CervinoAlejandro RibeiroNageen HimayatFEI: Fusion Processing of Sensing Energy and Information for Self-sustainable Infrared Smart Vision SystemAuthorsXin HongHaijin SuMaimaiti NazhamaitiCe ZhangJunkai HuangYuzhao YangLi LuoQi WeiZheyu LiuFei QiaoFrom RTL to Prompt: AN LLM-assisted Verification Methodology for General ProcessorAuthorsYifei DengChao XiaoZhijie YangRenzhi ChenYuanfeng LuoJingyue ZhaoHuadong DaiLei WangYuhua TangWeixia XuFrom RTL to SVA: LLM-assisted generation of Formal Verification TestbenchesAuthorsMarcelo Orenes-VeraMargaret MartonosiDavid WentzlaffGNN-Opt: Enhancing Automated Circuit Design Optimization with Graph Neural NetworksAuthorsKazuya YamamotoNobukazu TakaiGPU-Accelerated BFS for Dynamic NetworksAuthorsFilippo ZicheRosalba GiugnoFederico BusatoNicola BombieriOptimization of DSP-Based Equalizer in High-Speed ADC-Based ReceiversAuthorsYoona LeeHanseok KimJin-Seok HeoWoo-Seok ChoiHPA: A novel IS-WS hybrid data flow for PIM architecturesAuthorsYun ZhaoSheng MaHeng LiuLi HuangLi WuJian ZhangChun ZhangTie LiHyft: A Reconfigurable Softmax Accelerator with Hybrid Numeric Format for both Training and InferenceAuthorsTianhua XiaSai Qian ZhangIntegrated MAC-based Systolic Arrays: Design and Performance EvaluationAuthorsDantu Nandini DeviGandi Ajay KumarBindu G GowdaMadhav RaoInteractive Visual Performance Space Exploration of Analog ICs with Neural Network Surrogate ModelsAuthorsYannick UhlmannTill MoldenhauerJürgen ScheibleLabidus: Productive Accelerator Development via Configurable Soft ProcessorsAuthorsGongjin SunSeongyoung KangJane HeSang-Woo JunLEAP: Layout aware Estimation of Analog design ParasiticsAuthorsPrasanth MangalagiriSiddhartha JoshiLearned Index Acceleration with FPGAs: A SMART ApproachAuthorGeetesh MoreLibra: Collaborating with Basis-Inverted Circuits to Mitigate State-Dependent Errors on NISQ ProgramsAuthorsEnhyeok JangYoungmin KimWon Woo RoMatHE: A Near-Mat Processing In-Memory Accelerator for Fully Homomorphic EncryptionAuthorsMinxuan ZhouYujin NamPranav GangwarWeihong XuArpan DuttaChris WilkersonRosario CammarotaSaransh GuptaTajana RosingMethodology of configurable memory conflict-free Number Theoretic Transform accelerator for FPGA platformAuthorsXiangchen MengYangdi LyuMulti-modal Signal applied Dynamic neuron based Spike processor for Stress DetectionAuthorsAjay BSPhani PavanMadhav RaoMulti-modal Signal applied Neuromorphic proven SNN Model for Stress DetectionAuthorsAjay BSMadhav RaoNavigating the Challenges of Statistical Fault Injection in SRAM-FPGAAuthorsTrishna RajkumarJohnny ObergNeuCore: A Novel Neuromorphic Processor Architecture with On-chip Event-driven LearningAuthorsYi Weizhijie YangXun Xiaoxiangyu Wangjunbo Tiejingyue ZhaoLei Wanghuadong DaiWeixia XuYuhua TangZhenhua ZhuNeuroSteiner: A Graph Transformer for Wirelength EstimationAuthorsSahil ManchandaDana KianfarMarkus PeschlRomain LepertMichael DefferrardnvmXR: Design Space Exploration of Non-Volatile Memory Architectures for Edge-XR SystemsAuthorsZihan ZhangMarco DonatoODILO: On-Device Incremental Learning Via Lightweight OperationsAuthorsQing WangDi LiuShengfa MiaoMingxiong ZhaoOn Optimization of Robustness of Inter- and Intra-chiplet Interconnection Topology for Multi-chiplet SystemsAuthorsMiao XuXiaohang WangAmit Kumar SinghYingtao JiangMei YangOperational Safety in Human-in-the-loop Human-in-the-plant Autonomous SystemsAuthorsAyan BanerjeeAranyak MaityImane LamraniSandeep GuptaOptimal Toffoli-Depth Quantum AdderAuthorsSiyi WangAnkit MondalAnupam ChattopadhyayOptimizing Homomorphic Convolution for Private CNN InferenceAuthorsHyeri RohWoo-Seok ChoiPIANIST: Efficient Quantum Circuit Simulation using Commercial Processing-in-Memory SystemAuthorsDongin LeeEnhyeok JangSeungwoo ChoiJunwoong AnCheolhwan KimWon Woo RoPixelPrune: Sparse Object Detection for AIoT Systems via In-Sensor Segmentation and Adaptive Data TransferAuthorsMohammadReza MohammadiMehrdad MorsaliBrendan ReidySepehr TabrizchiMohsen ImaniArman RoohiShaahin AngiziRamtin ZandPre-Silicon Power Side-channel Leakage Assessment of CRYSTALS-KyberAuthorsNashmin AlamTao ZhangFarimah FarahmandiPrinciples for Enabling TEEs on Domain-Specific AcceleratorsAuthorsAritra DharSupraja SridharaShweta ShindeSrdjan CapkunRenzo AndriPushing Computing-in-memory towards Computational Storage to Accelerate In-Orbit Remote Sensing Satellite Image ProcessingAuthorsHongyang HuShengwen LiangKai XiZizhen LiuJinshan YueDashan ShangXiaoxin XuJing LiuChunmeng DouMing LiuQuantifying the Energy Efficiency Benefits of Monolithic 3D Refreshless Embedded-DRAMAuthorsDavid KongShvetank PrakashJedrzej KufelGeorgios KyriazidisYasmine OmriDavid VerityEmre OzerVijay Janapa ReddiGage HillsQuantization Noise Cancellation Through Modelling of Non-Linearities in Sigma Delta ModulatorsAuthorsStijn RingelingMarco FattoriShagun BajoriaRobert RuttenLucien BreemsEugenio CantatoreQuBound: An Efficient Workflow Enabling Prediction of Performance Bounds under Unpredictable Quantum NoiseAuthorsjinyang liSamudra DasguptaTravis HumbleWeiwen JiangRADAR: A Skew-resistant and Hotness-aware Ordered Index Design for Processing-in-memory SystemsAuthorsYifan HuaShengan ZhengWeihan KongCong ZhouKaixin HuangRuoyan MaYifeng HuiLinpeng HuangRepresentation-Independent Resubstitution for Area-Oriented Logic OptimizationAuthorsAndrea CostamagnaAlessandro Tempia CalvinoAlan MishchenkoSatrajit ChatterjeeSiang-Yun LeeGiovanni De MicheliReset Domain Crossing Design Verification Closure using Advanced Data Analytics TechniquesAuthorsREETIKA REETIKASulabh KhareSASDynabLE: A Compact Transformer Inference Architecture with Saturation-Approximate Softmax Enabling Dynamic-Mapping Based Layer-Fusion ExecutionAuthorsLiu HeZongle HuangYujin WangShupei FanTang ChenHuazhong YangYongpan LiuHongyang JiaScalable Multi-task Deep Inference on Resource Constrained Energy Harvesting SystemAuthorsSahidul IslamBin LeiShanglin ZhouChen PanCaiwen DingMimi XieScaler-FFT: A Scalable FPGA-based FFT Accelerator via General Matrix MultiplicationAuthorsSong ZhangZhiyuan MaZexu ZhangYueyin BaiKun WangSFQ counter-based precomputation for large-scale cryogenic VQE machinesAuthorsYosuke UenoSatoshi ImamuraYuna TomidaTeruo TanimotoMasamitsu TanakaYutaka TabuchiKoji InoueHiroshi NakamuraSI-Aware Wire Timing Prediction at Pre-Routing Stage with Multi-Corner ConsiderationAuthorsXu HeYushan WangRenjun ZhaoYao WangChang LiuYang GuoSoCureLLM: An LLM-driven Approach for Large-Scale System-on-Chip Security Verification and Policy GenerationAuthorsShams TarekDipayan SahaSujan Kumar SahaMark TehranipoorFarimah FarahmandiSPHINCSLET - A Lightweight Implementation of SPHINCS+AuthorsSanjay DeshpandeYongseok LeeCansu KarakuzuJakub SzeferYunheung PaekTDM: Time and Distance based Metric for Quantifying Information Leakage Vulnerabilities in SoCsAuthorsAvinash AyalasomayajulaHasan Al-ShaikhHenian LiSujan SahaFarimah FarahmandiThe Power of Graph Signal Processing for Chip PlacementAuthorsYiting LiuHai ZhouJia WangFan YangXuan ZengLi ShangTinySeg: Memory-efficient Image Segmentation for Small Embedded SystemsAuthorsByungchul ChaeJiae KimSeonyeong HeoTRIFP-DCIM: A Toggle-Rate-Immune Floating-point Digital Compute-in-Memory Design with Adaptive-Asymmetric Compute-TreeAuthorsXing WangTianhui JiaoYuchen MaZhican ZhangZhichao LiuXi ChenXin SiTripartite Server Mutual Attestation: TEE-based BFT for Boosting Server Reliability in Federated LearningAuthorsYusen WuPhuong NguyenYelena YeshaUnderstanding the Upper Bounds of Energy Efficiency in a Computing-in-Memory Processor and How to Approach the LimitAuthorsZhaori CongJinshan YueShengzhe YanZhuoyu DaiZeyu GuoZhihang QianYifan Hesun wenyuChunmeng DouFeng ZhangYongpan LiuVisionHD: Revisiting Hyperdimensional Computing for Improved Image ClassificationAuthorsFatemeh AsgarinejadJustin MorrisTajana RosingBaris AksanliWhere and How to Charge: Effective Charging with Mobile Agent in Wireless Powered CPSAuthorsChenchen FuZining ZhouSujunjie SunWeiwei WuSong Han
