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Work-in-Progress Poster: Wednesday Work-in-Progress Posters
Event TypeWork-in-Progress Poster
TimeWednesday, June 266:00pm - 7:00pm PDT
LocationLevel 2 Lobby
Topics
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Presentations
A Crosstalk-Aware Timing Prediction Method in Routing
A Divide-and-conquer Pebbling Strategy for Oracle Synthesis in Quantum Computing
A DRAM-based PIM Architecture for Accelerated and Energy-Efficient Execution of Transformers
A Fast IR-drop Modeling for In-RRAM Computing Considering Data Allocation
A Multi-objective Optimization Framework of Spiking Neural Network and Neuromorphic Processor
A Near-data Processing Architecture for GNN Training and Inference Acceleration
A New Iterative Method with Krylov Subspace Recycling for Efficient Periodic AC and Noise Analysis
A Novel Approach: Applying Fractional Factorial Design Methodology to Stress-Map, Experimental Study for Stress-Induced Failure (Bug), and Stress Coverage Assessment in Post-Silicon Validation Process
A Practical DRAM-based Analog PIM Architecture
A verification plan to assess the quality of mobile telephony in Brazil
Accelerating DNN Execution via Weight and Data Adaptive N:M Pruning
Accelerating Heterogeneous Workloads Using A Reconfigurable In-Memory Computing Architecture
Accelerating Large-scale Sparse LU Factorization for RF Circuit Simulation
Accelerating Range-Joins for Big Data Genomic Variant Annotation on HBM-enabled FPGAs
AdaP-CIM: Compute-in-Memory Based Neural Network Accelerator using Adaptive Posit and Speculative Alignment
Adaptive Graph Learning for Efficient Thermal Analysis of the Chiplet System under Interface Variations
Advanced Analog Design Optimization: Comparison Between Reinforcement Learning and Heuristic Algorithms
Affinity-based Optimizations of Homomorphic Encryption Operations on Processing-in-DRAM
Agile Discovery of Efficient Real-Time Systems-on-Chips in the Heterogeneous Era
An Efficient and Scalable Clocking Assignment Algorithm for Multi-Threaded Multi-Phase Single Flux Quantum Circuits
An Efficient Framework for High-Fidelity Automotive Exterior Design
An instant leafcell layout auto-generator for area compact memory design automation
An Open-Source Framework for AMS Modeling and Verification
Analysis of 64-bit Parallel Prefix Adders and 32-bit Matrix Multiply Units Designed with 7-nm CNFET
ATAFAN: Design-Friendly Aging-aware Timing Analysis Framework Based on Hybrid Graph Network
CIM for LLM: A Compute-In-Memory Architecture for Efficient Large Language Model Inference
CIMAP: A CIM Crossbar Array Data Mapping Methodology for Unstructured Sparse Convolutional Neural Networks
Circuit Transformer: End-to-end Logic Synthesis by Predicting the Next Gate
Stability Analysis of Integrated Circuits via Graph Neural Networks
Compressed Latent Replays for Lightweight Continual Learning on Spiking Neural Networks
Compression with Attention: Learning in Lower Dimensions
Confidential Computing with Heterogeneous Devices at Cloud-Scale
DATIS: DRAM Architecture and Technology Integrated Simulation
DB-Hunter: Interactive-Guided Differential Testing for FPGA Simulation Debugger
Defending Membership Inference Attack on Edge using Trusted Execution Environments
Distributed Inference of DL Workloads on CIM-based Heterogeneous Accelerators
Distribution-Guided Fairness Calibration in Learning
DNNPhaser: Enhancing Data Locality Using Multiphase Ring Dataflow for Spatial Accelerators
DOCTOR: Dynamic On-Chip Remediation Against Temporally-Drifting Thermal Variations Toward Self-Corrected Photonic Tensor Accelerators
Don't Cache, Speculate!: Speculative Address Translation for Flash-based Storage Systems
DRL-based Voltage Optimization for Multiple Droplet Routing in DMFBs
DTrans: A Dataflow-transformation FPGA Accelerator with Nonlinear-operators fusion aiming for the Generative Model
Dual-Axis ECC: Vertical and Horizontal error correction
Efficient Prediction of SRAM Read Access Time and Yield via Neural Network Leveraging Transfer Learning and Transformer Models
EffiPipe: Towards Energy-Efficient Large-scale Model Training on Commodity GPUs
Eliminate control divergence in SpMV via in-SRAM reduction
Evergreen: Comprehensive Carbon Modeling for Performance-Emission Tradeoffs
FOTA-Quant: FPGA-Oriented Token Adaptive Quantization Framework for the Acceleration of LLMs
Fully Automated Implementation of Reservoir Computing Models on FPGAs for Nanosecond Inference Times
GL0AM: GPU Logic Simulation Using 0-Delay and Re-simulation Acceleration Method
Graph Attention Network-based Sparse Format Selection for Accelerating SpMM on GPUs
H4H: Hybrid Convolution-Transformer Architecture Search for NPU-CIM Heterogeneous Systems for AR/VR Applications
Hardware PDE Solvers Using Dynamic Stochastic Computing
HDFusion: Hierarchical Data Fusion for Robust Deep Tissue Sensing
Heterogeneous Vector Accelerator for Matrix Multiplications on FPGA
High-Performance Remote Data Persisting for Key-Value Stores via Persistent Memory Region
HRing: A Hierarchical Ring Design Method for Wavelength-Routed Optical Networks-on-Chip
Hybrid Stochastic Computing of Linear Time O(N) and Its In-Memory Computing for High Performances
Hydrogen: Contention-Aware Hybrid Memory Management for Heterogeneous CPU-GPU Architectures
Enhancing Delay-driven LUT Mapping with Boolean Decomposition
Instruction Sequence Generation using Reinforcement Learning for Software-Based Self-Test of Processor Cores
Knowledge is Power: A Knowledge-Guided Oracle-Less Attack on Logic Locking
LUTMUL: A Paradigm Shift from DSPs to LUTs for Efficient Multiplication in FPGA-Based Neural Network Computation
TUNE: Transformer-based Unified NEtwork for Bidirectional Prediction between Circuit Parameters and Specifications
MAM-CIM: Data Resilience Scheduling Based Multilevel Analog Memory for Near Sensor Computing-In-Memory Architecture
Mining signal temporal logic specifications for hybrid systems
mROB: Multi-Level ReOrder Buffer Design with Reduced Area and Power
Multi-Terminal Pathfinding with Conditional Denoising Diffusion Probabilistic Model
PABTG: A Pipeline Architecture for Beaver Triple Generation in Secure Multi-party Computation
PCBench: A Dataset for Printed Circuit Board Routing
PINN-based Compact Model for On-chip Silicon Photonic Devices
P-ReTi: Photonic Tensor Core for Real-Time Learning
Probability Modeling for Via-Metal Open Circuit Defects Utilizing Self-Aligned Vias Process in 5nm Technology Node and Beyond
QPulse: Ansatz Design Analysis and Advantages of Parameterized Quantum Pulses
Transformer-QEC: Quantum Error Correction Code Decoding with Transferable Transformers
ReS-CIM: ReRAM-cached SRAM Compute-in-Memory Architecture with a Differential Sensing Scheme Enabling Intra-Macro Weight Loading
Rethinking DRAM Failure Prediction In Memory Reliability: An Efficient Deep Image Classification Perspective
Retract: Logarithmic-Depth Reconstruction of Continuous Controlled-NOT Logic Block
RobustState: Boosting Fidelity of Quantum State Preparation via Noise-Aware Variational Training
SeGen: Automatic Topology Generator of Sequencing Element
Shared-PIM: Enabling Concurrent Computation and Data Flow for Faster Processing-in-Memory
Solving Maximum Flows of Undirected Graphs by Minimizing s-t Effective Resistances of Electrical Networks
SPulseGen: Succinct pulse generator architecture maximizing gate fidelity for superconducting quantum computers
SVDE: Serverless System for Low-Latency Video Analytic Queries Using Tree-based Regression
TACPlace: Ultrafast Thermal-Aware Chiplet Placement under Multi-Power Mode Using Feasibility Seeking
Enhancing Edge Computing with In/Near-Sensor Processing Schemes for Vision Transformers
Worst Case Response Time Analysis for Completely Fair Scheduling in Linux Systems
xPMEM: A Design of Byte-Addressable Persistent Memory with Compute Express Link for Advanced Data Center Applications
Zero-Space Cost Fault Tolerance for Transformer-based language models on ReRAM
Automated Generation of OoO ASIP from ISA Documents via Nano-Operator Abstraction