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UID:dac_DAC 2024_sess102_RESEARCH965@linklings.com
SUMMARY:Less is More: Hop-Wise Graph Attention for Scalable and Generaliza
 ble Learning on Circuits
DESCRIPTION:Research Manuscript\n\nChenhui Deng and Zichao Yue (Cornell Un
 iversity); Cunxi Yu (University of Maryland, College Park); Gokce Sarar, R
 yan Carey, and Rajeev Jain (Qualcomm); and Zhiru Zhang (Cornell University
 )\n\nWhile graph neural networks (GNNs) have gained popularity for learnin
 g circuit representations in various electronic design automation (EDA) ta
 sks, they face challenges in scalability when applied to large graphs and 
 exhibit limited generalizability to new designs. These limitations make th
 em less practical for addressing large-scale, complex circuit problems. In
  this work we propose HOGA, a novel attention-based model for learning cir
 cuit representations in a scalable and generalizable manner. HOGA first co
 mputes hop-wise features per node prior to model training. Subsequently, t
 he hop-wise features are solely used to produce node representations throu
 gh a gated self-attention module, which adaptively learns important featur
 es among different hops without involving the graph topology. As a result,
  HOGA is adaptive to various structures across different circuits and can 
 be efficiently trained in a distributed manner. To demonstrate the efficac
 y of HOGA, we consider two representative EDA tasks: quality of results (Q
 oR) prediction and functional reasoning. Our experimental results indicate
  that (1) HOGA reduces estimation error over conventional GNNs by 46.76% f
 or predicting QoR after logic synthesis; (2) HOGA improves 10.0% reasoning
  accuracy over GNNs for identifying functional blocks on unseen gate-level
  netlists after complex technology mapping; (3) The training time for HOGA
  almost linearly decreases with an increase in computing resources.\n\nTop
 ic: AI\n\nKeyword: AI/ML Algorithms\n\nSession Chairs: Parivesh Choudhary 
 (Synopsys) and Anca Molnos (CEA-List)
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