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DTSTAMP:20240626T180033Z
LOCATION:3003\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240626T164500
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UID:dac_DAC 2024_sess110_RESEARCH021@linklings.com
SUMMARY:PHD: Parallel Huffman Decoder on FPGA for Extreme Performance and 
 Energy Efficiency
DESCRIPTION:Research Manuscript\n\nYunkun Liao, Jingya Wu, Wenyan Lu, Xiao
 wei Li, and Guihai Yan (State Key Lab of Processors, Institute of Computin
 g Technology, Chinese Academy of Sciences)\n\nHuffman decoding is crucial 
 in data compression, and the self-synchronization-based parallel decoding 
 algorithm enables subsequence-level parallelism. This paper introduces PHD
 , the first accelerator designed for self-synchronization-based parallel H
 uffman decoding on the Field-Programmable Gate Array (FPGA). Designing PHD
  poses challenges, including managing fine-grained parallelism, addressing
  limited on-chip memory, and handling inter-codeword dependency. PHD incor
 porates bit-level, subsequence-level, and tile-level parallelism, utilizes
  hybrid memory to store the codebook efficiently, and introduces the ONCE 
 MORE optimization to reduce decoding loop iterations. Experimental results
  demonstrate that PHD outperforms the state-of-the-art GPU-based baseline 
 regarding latency (9.4X to 12.8X reduction) and energy consumption (12.4X 
 to 18.2X reduction).\n\nTopic: Design\n\nKeyword: SoC, Heterogeneous, and 
 Reconfigurable Architectures\n\nSession Chairs: Jason Anderson (University
  of Toronto) and Andrea Guerrieri (École Polytechnique Fédérale de Lausann
 e)
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