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UID:dac_DAC 2024_sess110_RESEARCH1366@linklings.com
SUMMARY:Chiplever: Towards Effortless Extension of Chiplet-based System fo
 r FHE
DESCRIPTION:Research Manuscript\n\nYibo Du (Institute of Computing Technol
 ogy, Chinese Academy of Sciences); Ying Wang (State Key Laboratory of Comp
 uter Architecture, Institute of Computing Technology, Chinese Academy of S
 ciences, University of Chinese Academy of Sciences); Bing Li (Capital Norm
 al University); Fuping Li (State Key Laboratory of Computer Architecture, 
 Institute of Computing Technology, Chinese Academy of Sciences, University
  of Chinese Academy of Sciences); Shengwen Liang (State Key Lab of Process
 ors, Institute of Computing Technology, Chinese Academy of Sciences); and 
 Huawei Li, Xiaowei Li, and yinhe han (Institute of Computing Technology, C
 hinese Academy of Sciences)\n\nFully Homomorphic Encryption (FHE) is one o
 f the most promising privacy-preserving techniques, which has drawn increa
 sing attention from both academia and industry due to its ideal security. 
 Chiplet-based designs integrate multiple dies (chiplet) into the package d
 elivering high performance and thereby are embraced by the resources-hungr
 y FHE. Despite the chiplet-based system with various specialized accelerat
 ors, it falls short in supporting FHE due to the novel FHE polynomial oper
 ations. For a chiplet-based system that is not tailored for FHE, one commo
 n approach to make it capable of FHE is designing a new dedicated accelera
 tor, However, this full design-and-build approach overlooks the existing a
 bundant resources of accelerators in the system and thereby incurs repeate
 d customization and resource waste. \nIn this paper, we propose Chiplever,
  a framework enables effortless extension of Chiplet-based system for FHE.
   We aim to fully harness the available resources in the room for efficien
 t FHE. To achieve this, Chiplever (1)introduces a specialized extension in
  I/O Chiplet guided by semantics matching (2)and proposes an efficient all
 ocator featuring specialized dataflow scheduling. (3)Chiplever provides th
 ree-step mapping to achieve compiler-level to hardware-level support for F
 HE and optimizes the data communications.\n\nTopic: Design\n\nKeyword: SoC
 , Heterogeneous, and Reconfigurable Architectures\n\nSession Chairs: Jason
  Anderson (University of Toronto) and Andrea Guerrieri (École Polytechniqu
 e Fédérale de Lausanne)
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