BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20240626T180034Z
LOCATION:3012\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240625T154500
DTEND;TZID=America/Los_Angeles:20240625T160000
UID:dac_DAC 2024_sess112_RESEARCH1312@linklings.com
SUMMARY:WinoGen: A Highly Configurable Winograd Convolution IP Generator f
 or Efficient CNN Acceleration on FPGA
DESCRIPTION:Research Manuscript\n\nMingjun Li (The Chinese University of H
 ong Kong); Pengjia Li (The Chinese University of Hong Kong, Shenzhen); Shu
 o Yin, Shixin Chen, and Beichen Li (The Chinese University of Hong Kong); 
 Chong Tong (The Chinese University of Hong Kong, Shenzhen); Jianlei Yang (
 Beihang University); Tinghuan Chen (The Chinese University of Hong Kong, S
 henzhen); and Bei Yu (The Chinese University of Hong Kong)\n\nThe convolut
 ion neural network (CNN) has been widely adopted in computer vision tasks.
  \n    In the FPGA-based CNN accelerator design, Winograd convolution can 
 effectively improve computation performance and save hardware resources.\n
     However, building efficient and highly compatible IP for arbitrary Win
 ograd convolution on FPGA remains underexplored.\n    To address this issu
 e, we propose a novel and efficient reformulation of Winograd convolution,
  named Structured Direct Winograd Convolution (SDW).\n    We further devel
 op WinoGen, a Chisel-based highly configurable Winograd convolution IP gen
 erator. \n    Given arbitrary input/output tile size and kernel size, it c
 an generate optimized high-performance IP automatically. \n    Meanwhile, 
 our generated IP can be compatible with multiple kernel sizes and tile siz
 es.\n    Experimental results show that the IP generated by WinoGen achiev
 es DSP efficiency up to 3.80 GOPS/DSP and energy efficiency up to 652.77 G
 OPS/W while showing 2.45 times and 3.10 times improvements when processing
  a same CNN model compared with state-of-the-arts.\n\nTopic: Design\n\nKey
 word: SoC, Heterogeneous, and Reconfigurable Architectures\n\nSession Chai
 rs: Dimitrios Soudris (National Technical University of Athens) and George
  Tzimpragos (University of Michigan)
END:VEVENT
END:VCALENDAR