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DTSTART:19700308T020000
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DTSTAMP:20240626T180033Z
LOCATION:3003\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240627T150000
DTEND;TZID=America/Los_Angeles:20240627T151500
UID:dac_DAC 2024_sess117_RESEARCH649@linklings.com
SUMMARY:TIGA: Towards Efficient Near Data Processing in SmartNICs-based Di
 saggregated Memory Systems
DESCRIPTION:Research Manuscript\n\nZhuohui Duan, Zelin Yu, Haikun Liu, Xia
 ofei Liao, Hai Jin, Shijie Zheng, and Sihan Wu (Huazhong University of Sci
 ence and Technology)\n\nMemory disaggregation, facilitated by SmartNICs, h
 as emerged as a cost-effective approach for sharing memory resources in da
 ta centers. However, current SoC-based SmartNICs face several challenges f
 or supporting near-data processing (NDP) in DM systems effectively. To add
 ress these challenges, we propose TIGA, an efficient NDP framework for Sma
 rtNICs-based DM systems. We propose an adaptive resource allocator to full
 y utilize SoC cores, and a SmartNIC-CPU cooperative mechanism to schedule 
 NDP tasks. We prototype TIGA with FPGAs and evaluate it with typical workl
 oads. Experimental results show that TIGA significantly improves the effic
 iency of NDP tasks in DM systems.\n\nTopic: Design\n\nKeyword: In-memory a
 nd Near-memory Computing Circuits\n\nSession Chair: Shubham Jain (IBM Thom
 as J. Watson Research Center)
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