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UID:dac_DAC 2024_sess118_RESEARCH991@linklings.com
SUMMARY:Efficient Memory Integration: MRAM-SRAM Hybrid Accelerator for Spa
 rse On-Device Learning
DESCRIPTION:Research Manuscript\n\nFan Zhang (Johns Hopkins University), A
 mitesh Sridharan (Arizona State University), Wilman tsai (Stanford Univers
 ity), Yiran Chen (Duke University), Shan Wang (Stanford University), and D
 eliang Fan (Johns Hopkins University)\n\nWith the prosperous development o
 f Deep Neural Network (DNNs), numerous Process-In-Memory (PIM) designs hav
 e emerged to accelerate DNN models with exceptional throughput and energy-
 efficiency.  PIM accelerators based on Non-Volatile Memory (NVM) or volati
 le memory offer distinct advantages for computational efficiency and perfo
 rmance. NVM based PIM accelerators, demonstrated success in DNN inference,
  face limitations in on-device learning due to high write energy, latency,
  and instability. Conversely, fast volatile memories, like SRAM, offer rap
 id read/write operations for DNN training, but suffer from significant lea
 kage currents and large memory footprints. In this paper, for the first ti
 me, we present a fully-digital sparse processing in hybrid NVM-SRAM design
 , synergistically combines the strengths of NVM and SRAM, tailored for on-
 device continual learning. Our designed NVM and SRAM based PIM circuit mac
 ros could support both storage and processing of N:M structured sparsity p
 attern, significantly improving the storage and computing efficiency. Exha
 ustive experiments demonstrate that our hybrid system effectively reduces 
 area and power consumption while maintaining high accuracy, offering a sca
 lable and versatile solution for on-device continual learning.\n\nTopic: D
 esign\n\nKeyword: In-memory and Near-memory Computing Architectures, Appli
 cations and Systems\n\nSession Chairs: Seokhyeong Kang (Pohang University 
 of Science and Technology (POSTECH)) and Giacomo Pedretti (Hewlett Packard
  Enterprise)
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