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DTSTAMP:20240626T180033Z
LOCATION:3003\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240626T133000
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UID:dac_DAC 2024_sess125_RESEARCH774@linklings.com
SUMMARY:PIVOT- Input-aware Path Selection for Energy-efficient ViT Inferen
 ce
DESCRIPTION:Research Manuscript\n\nAbhishek Moitra, Abhiroop Bhattacharjee
 , and Priyadarshini Panda (Yale University)\n\nThe sophisticated self-atte
 ntion-based spatial correlation entails a high inference delay cost in vis
 ion transformers. To this end, we propose PIVOT-a hardware-algorithm co-op
 timization framework for input-difficulty-aware attention skipping for att
 ention bottleneck optimization. The attention-skipping configurations are 
 obtained via an iterative hardware-in-the loop co-search method. On the ZC
 U102 MPSoC FPGA, PIVOT achieves 2.7×(1.73×) lower EDP at 0.2%(0.4%) accura
 cy reduction compared to standard LVViT-S (DeiT-S) ViTs. Unlike prior work
 s that require nuanced hardware support, PIVOT is compatible with traditio
 nal GPU and CPU platforms- 1.8× higher throughput at 0.4-1.3% higher accur
 acy compared to prior works.\n\nTopic: AI, Design\n\nKeyword: AI/ML System
  and Platform Design\n\nSession Chairs: Amin Firoozshahian (Rain AI) and T
 hierry Tambe (Stanford University)
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