BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:3002\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240625T164500
DTEND;TZID=America/Los_Angeles:20240625T170000
UID:dac_DAC 2024_sess130_RESEARCH1363@linklings.com
SUMMARY:Unleashing the Power of T1-cells in SFQ Arithmetic Circuits
DESCRIPTION:Research Manuscript\n\nRassul Bairamkulov, Mingfei Yu, and Gio
 vanni De Micheli (École Polytechnique Fédérale de Lausanne)\n\nSuperconduc
 tive rapid single-flux quantum (RSFQ) ICs dissipate 10-100 smaller power w
 .r.t. CMOS while operating at tens of GHz. The issue of path balancing in 
 RSFQ systems however incurs significant area overhead, particularly severe
  due to limited layout density of RSFQ fabrication.\n\nThe SFQ T1-cell rea
 lize the full adder function with 60% less area compared to conventional i
 mplementation. This cell however imposes complex input timing constraints.
  With multiphase clocking, the T1-cell input timing can be efficiently sat
 isfied. Here, we propose SFQ technology mapping methodology supporting T1-
 cells. The area of the arithmetic SFQ networks is reduced by up to 25%.\n\
 nTopic: Design\n\nKeyword: Emerging Models of Computation\n\nSession Chair
 s: Dharanidhar Dang (The University of Texas at San Antonio) and Jiyong Wo
 o (Kyungpook National University)
END:VEVENT
END:VCALENDAR
