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DTSTAMP:20240626T180002Z
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DTSTART;TZID=America/Los_Angeles:20240626T103000
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UID:dac_DAC 2024_sess142@linklings.com
SUMMARY:Analog Design Verification and Layout Synthesis Rethought
DESCRIPTION:Research Manuscript\n\nThis session solves core EDA problems f
 or analog circuit design. The first five papers improve verification start
 ing with advanced simulation methods for complex (extracted) circuits: sim
 ulations are empowered by a memory-efficient solution for sparse matrices 
 and a powerful graph sparsification algorithm; an efficient capacitance ap
 proximation methodology is proposed to enhance parasitic extraction while 
 PCB-S-parameters are modeled by an AI-driven estimator; and a gradient des
 cent approach improves equivalence checking. Finally, an AI approach tackl
 es the analog layout synthesis problem with 3DGNNs.\n\nEnhancing 3-D Rando
 m Walk Capacitance Solver with Analytic Surface Green's Functions of Trans
 ition Cubes\n\nThe complicated dielectric profile under advanced process t
 echnologies challenges the accuracy of floating random walk (FRW) based ca
 pacitance extraction, as the latter pre-computes the surface Green's funct
 ions for a finite set of multi-dielectric transition cubes and makes appro
 ximations of transi...\n\n\nJiechen Huang and Wenjian Yu (Tsinghua Univers
 ity)\n---------------------\nMASC: A Memory-Efficient Adjoint Sensitivity 
 Analysis through Compression Using Novel Spatiotemporal Prediction\n\nAdjo
 int sensitivity analysis is critical in modern integrated circuit design a
 nd verification, but its computational intensity grows significantly with 
 the size of the circuit, the number of objective functions, and the accumu
 lation of time points. This growth can impede its wider application. The i
 ...\n\n\nChenxi Li (Super Scientific Software Laboratory, China University
  of Petroleum-Beijing); Boyuan Zhang (Indiana University, Bloomington); Yo
 ngqiang Duan and Yang Li (Super Scientific Software Laboratory, China Univ
 ersity of Petroleum-Beijing); Zuochang Ye (Tsinghua University); Weifeng L
 iu (Super Scientific Software Laboratory, China University of Petroleum-Be
 ijing); Dingwen Tao (Indiana University, Bloomington); and Zhou Jin (Super
  Scientific Software Laboratory, China University of Petroleum-Beijing)\n-
 --------------------\ninGRASS: Incremental Graph Spectral Sparsification v
 ia Low-Resistance-Diameter Decomposition\n\nThis work presents inGRASS, a 
 novel algorithm designed for incremental spectral sparsification of large 
 undirected graphs. The proposed inGRASS algorithm is highly scalable and p
 arallel-friendly, having a nearly linear time complexity for the setup pha
 se and the ability to update the spectral sparsi...\n\n\nAli Aghdaei and Z
 huo Feng (Stevens Institute of Technology)\n---------------------\nTraceFo
 rmer: S-parameter Prediction Framework for PCB Traces based on Graph Trans
 former\n\nSignal integrity becomes more critical to modern digital systems
  such as solid-state drives due to their high-speed operation. However, on
 e of the challenges in signal integrity analysis is S-parameter modeling p
 rocess for printed circuit boards (PCB). Due to increasing PCB design comp
 lexity, existi...\n\n\nDoyun Kim, Jaemin Park, Youngmin Oh, and Bosun Hwan
 g (Samsung)\n---------------------\nEfficient Equivalence Checking of Nonl
 inear Analog Circuits using Gradient Ascent\n\nIn this paper, we present a
 n optimized methodology for performing state-space-based equivalence check
 ing of nonlinear analog circuits by using a gradient-ascent-based search a
 lgorithm to efficiently traverse a common state space. Essentially, the me
 thod searches for critical regions where the functi...\n\n\nKemal Çağlar C
 oşkun and Muhammad Hassan (University of Bremen), Lars Hedrich (Goethe Uni
 versity Frankfurt), and Rolf Drechsler (University of Bremen)\n-----------
 ----------\nPerformance-driven Analog Routing via Heterogeneous 3DGNN and 
 Potential Relaxation\n\nAnalog routing is crucial for performance optimiza
 tion in analog circuit design, but conventionally takes significant develo
 pment time and requires design expertise. Recent research has attempted to
  use machine learning (ML) to generate guidance to preserve circuit perfor
 mance after analog routing. ...\n\n\nPeng Xu, Guojin Chen, and Keren Zhu (
 The Chinese University of Hong Kong); Tinghuan Chen (The Chinese Universit
 y of Hong Kong, Shenzhen); and Tsung-Yi Ho and Bei Yu (The Chinese Univers
 ity of Hong Kong)\n\nTopic: EDA\n\nKeyword: Analog CAD, Simulation, Verifi
 cation and Test\n\nSession Chairs: Weidong Cao (Washington University, St.
  Louis) and Ahmet Budak (Analog Devices, Inc. (ADI))
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