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DTSTAMP:20240626T180033Z
LOCATION:3010\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240626T113000
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UID:dac_DAC 2024_sess142_RESEARCH328@linklings.com
SUMMARY:Efficient Equivalence Checking of Nonlinear Analog Circuits using 
 Gradient Ascent
DESCRIPTION:Research Manuscript\n\nKemal Çağlar Coşkun and Muhammad Hassan
  (University of Bremen), Lars Hedrich (Goethe University Frankfurt), and R
 olf Drechsler (University of Bremen)\n\nIn this paper, we present an optim
 ized methodology for performing state-space-based equivalence checking of 
 nonlinear analog circuits by using a gradient-ascent-based search algorith
 m to efficiently traverse a common state space. Essentially, the method se
 arches for critical regions where the functional behaviors of two circuit 
 designs show the greatest divergence. The key challenges in this approach 
 are the mapping of both designs onto a common canonical state space, the c
 omputation of the gradient, and the exclusion of unreachable regions withi
 n the state space. To address the first challenge, we use locally lineariz
 ed systems and leverage the Kronecker Canonical Form (KCF). To facilitate 
 the computation of the gradient, we employ a purpose-built target function
 , and to exclude unreachable regions, we utilize vector projection techniq
 ues. Through experiments with nonlinear analog circuits and a scalability 
 analysis, we demonstrate the successful and efficient computation performe
 d with the proposed methodology, achieving speedups of up to 468 times.\n\
 nTopic: EDA\n\nKeyword: Analog CAD, Simulation, Verification and Test\n\nS
 ession Chairs: Weidong Cao (Washington University, St. Louis) and Ahmet Bu
 dak (Analog Devices, Inc. (ADI))
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