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DTSTAMP:20240626T180033Z
LOCATION:3010\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240626T114500
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UID:dac_DAC 2024_sess142_RESEARCH722@linklings.com
SUMMARY:Performance-driven Analog Routing via Heterogeneous 3DGNN and Pote
 ntial Relaxation
DESCRIPTION:Research Manuscript\n\nPeng Xu, Guojin Chen, and Keren Zhu (Th
 e Chinese University of Hong Kong); Tinghuan Chen (The Chinese University 
 of Hong Kong, Shenzhen); and Tsung-Yi Ho and Bei Yu (The Chinese Universit
 y of Hong Kong)\n\nAnalog routing is crucial for performance optimization 
 in analog circuit design, but conventionally takes significant development
  time and requires design expertise. Recent research has attempted to use 
 machine learning (ML) to generate guidance to preserve circuit performance
  after analog routing. These methods face challenges such as expensive dat
 a acquisition and biased guidance. In this paper, we introduce AnalogFold,
  a new paradigm of analog routing leveraging ML-enabled performance-orient
 ed routing guidance. Our approach learns performance-driven routing guidan
 ce and uses it to help automatic routers for performance-driven routing op
 timization. We propose to use a 3DGNN that incorporates cost-aware distanc
 e to make accurate predictions on post-layout performance. A pool-assisted
  potential relaxation process derives the effective routing guidance. The 
 experimental results on multiple benchmarks under the TSMC 40nm technology
  node demonstrate the superiority of the proposed framework compared to th
 e cutting-edge works.\n\nTopic: EDA\n\nKeyword: Analog CAD, Simulation, Ve
 rification and Test\n\nSession Chairs: Weidong Cao (Washington University,
  St. Louis) and Ahmet Budak (Analog Devices, Inc. (ADI))
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