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DTSTART;TZID=America/Los_Angeles:20240627T150000
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UID:dac_DAC 2024_sess143_RESEARCH641@linklings.com
SUMMARY:PDRC: Package Design Rule Checking via GPU-Accelerated Geometric I
 ntersection Algorithms  for Non-Manhattan Geometry
DESCRIPTION:Research Manuscript\n\nJiaxi Jiang, Lancheng Zou, Wenqian Zhao
 , and Zhuolun He (The Chinese University of Hong Kong); Tinghuan Chen (The
  Chinese University of Hong Kong, Shenzhen); and Bei Yu (The Chinese Unive
 rsity of Hong Kong)\n\nWith the emergence of chiplet technology, the scale
  of IC packaging design has been steadily increasing, making the utilizati
 on of traditional design rule checking (DRC) methods more time-consuming. 
 In this paper, we propose PDRC, a package-level design rule checker for no
 n-manhattan geometry with GPU acceleration. \nPDRC employs hierarchical in
 terval lists within an iterative parallel sweepline framework to implement
  the geometric intersection algorithm, thereby finishing design rule check
 ing tasks.\nExperimental results have demonstrated 30 - 50 times speedup a
 chieved by PDRC\ncompared with two CPU-based checkers.\n\nTopic: EDA\n\nKe
 yword: Physical Design and Verification\n\nSession Chairs: Yu-Guang Chen (
 National Central University) and Vidya Chhabria (Arizona State University)
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