BEGIN:VCALENDAR VERSION:2.0 PRODID:Linklings LLC BEGIN:VTIMEZONE TZID:America/Los_Angeles X-LIC-LOCATION:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:19700308T020000 RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:19701101T020000 RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20240626T180002Z LOCATION:3010\, 3rd Floor DTSTART;TZID=America/Los_Angeles:20240626T153000 DTEND;TZID=America/Los_Angeles:20240626T173000 UID:dac_DAC 2024_sess144@linklings.com SUMMARY:On the Right Path: Navigating the Maze of Routing and Clock Tree Synthesis! DESCRIPTION:Research Manuscript\n\nYou have made it all the way here! So c ome hither and learn about the latest advanced algorithms to address the i ncreasingly complex signal and data routing challenges! These include a n ovel reinforcement learning-based approach for obstacle-aware Steiner tree s, an insightful pin-access co-optimization framework through on-the-fly s tandard cell pin layout regeneration, top-level design routing, minimal ar ea length matching for PCB routing, a priori resource allocation-based rou ter, a latency/load capacitance-centric approach for clock tree synthesis, and a GNN-assisted back-side clock routing algorithm.\n\nConcurrent Detai led Routing with Pin Pattern Re-generation for Ultimate Pin Access Optimiz ation\n\nPin access has become one of the most significant challenges in l arge-scale full-chip routing due to the continuous reduction in feature si zes and the increasing complexity of designs. The conventional standard ce ll layout synthesis approaches usually optimize pin accessibility by maxim izing pin len...\n\n\nYing-Jie Jiang and Shao-Yun Fang (National Taiwan Un iversity of Science and Technology)\n---------------------\nDGR: Different iable Global Router\n\nModern VLSI design flows necessitate fast and high- quality global routers. In this paper, we introduce DGR, a GPU-accelerated , differentiable global router capable of concurrent optimization for mill ions of nets, which we aim to open-source. Our innovation lies in the deve lopment of a routing Direct...\n\n\nWei Li (Carnegie Mellon University); R ongjian Liang, Anthony Agnesina, and Haoyu Yang (NVIDIA); Chia-Tung Ho (Un iversity of California, San Diego); and Anand Rajaram and Haoxing Ren (NVI DIA)\n---------------------\nArbitrary-size Multi-layer OARSMT RL Router T rained with Combinatorial Monte-Carlo Tree Search\n\nThis paper presents a novel reinforcement-learning-trained router for building a multi-layer ob stacle-avoiding rectilinear Steiner minimum tree (OARSMT). The router is t rained by our proposed combinatorial Monte-Carlo tree search to select a p roper set of Steiner points for OARSMT with only one infe...\n\n\nLiang-Ti ng Chen, Hung-Ru Kuo, Yih-Lang Li, and Mango C.-T. Chao (National Yang Min g Chiao Tung University)\n---------------------\nTop-Level Routing for Mul tiply-Instantiated Blocks with Topology Hashing\n\nModern System-on-Chip ( SoC) design is divided into hierarchical instances using the multiply-inst antiated block (MIB) technique to simplify the design process. Top-level r outing aims at providing routing prototyping between those instances. It r equires consideration of replicated routing paths that ...\n\n\nJiarui Wan g, Xun Jiang, and Yibo Lin (Peking University)\n---------------------\nObs tacle-Aware Length-Matching Routing for Any-Direction Traces in Printed Ci rcuit Board\n\nEmerging applications in Printed Circuit Board (PCB) routin g impose new challenges on automatic length matching, including adaptabili ty for any-direction traces with their original routing preserved for inte ractiveness. The challenges can be addressed through two orthogonal stages : assign non-overla...\n\n\nWeijie Fang, Longkun Guo, and Jiawei Lin (Fuzh ou University); xiong silu (Huawei); Huan He (Hangzhou Huawei Enterprises Telecommunication Technologies Co., LTD); Jiacen Xu (Shanghai LEDA Technol ogy Co., Ltd); and Jianli Chen (Fudan University)\n---------------------\n Net Resource Allocation: A Desirable Initial Routing Step\n\nIn modern IC design, routing significantly impacts chip performance, power, area, and d esign iteration count. Critical challenges in routing include generating rectilinear Steiner minimum tree (RSMT) for each net and handling routing resource among nets. Due to limited resources and net scale, cong...\n\n\n Zhisheng Zeng (State Key Lab of Processors, Institute of Computing Technol ogy, Chinese Academy of Sciences); Jikang Liu (Shenzhen University); Zhipe ng Huang (Peng Cheng Laboratory); Ye Cai (Shenzhen University); Biwei Xie and Yungang Bao (State Key Lab of Processors, Institute of Computing Techn ology, Chinese Academy of Sciences); and Xingquan Li (Peng Cheng Laborator y)\n---------------------\nGNN-assisted Back-side Clock Routing Methodolog y for Advance Technologies\n\nThe back-side metal layers exhibit lower par asitics compared to the front-side layers in advanced technologies, making them suitable for clock-net distribution. In this study, we explore the a dvantages of using back-side metal layers for clock routing, which is shar ed with a power delivery network. ...\n\n\nNesara Eranna Bethur and Pruek Vanna-iampikul (Georgia Institute of Technology); Odysseas Zografos (imec) ; Lingjun Zhu (Georgia Institute of Technology); Giuliano Sisto and Dragom ir Milojevic (imec); Alberto Garcia-Ortiz (University of Bremen); Geert He llings, Julien Ryckaert, and Francky Catthoor (imec); and Sung Kyu Lim (Ge orgia Institute of Technology)\n---------------------\nToward Controllable Hierarchical Clock Tree Synthesis with Skew-Latency-Load Tree\n\nClock tr ee synthesis (CTS) constructs an efficient clock tree, meeting design cons traints and minimizing resource usage. It serves as a bridge between place ment and routing, facilitating concurrent optimization of multiple design objectives. To construct a clock tree with lower latency and load capa...\ n\n\nWeiguo Li (Minnan Normal University), Zhipeng Huang (Peng Cheng Labor atory), Bei Yu (The Chinese University of Hong Kong), Wenxing Zhu (Fuzhou University), and Xingquan Li (Peng Cheng Laboratory)\n\nTopic: EDA\n\nKeyw ord: Physical Design and Verification\n\nSession Chairs: UDAY MALLAPPA (In tel Corporation) and Satish Sivaswamy (Advanced Micro Devices (AMD)) END:VEVENT END:VCALENDAR