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DTSTAMP:20240626T180035Z
LOCATION:3010\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240626T170000
DTEND;TZID=America/Los_Angeles:20240626T171500
UID:dac_DAC 2024_sess144_RESEARCH111@linklings.com
SUMMARY:Top-Level Routing for Multiply-Instantiated Blocks with Topology H
 ashing
DESCRIPTION:Research Manuscript\n\nJiarui Wang, Xun Jiang, and Yibo Lin (P
 eking University)\n\nModern System-on-Chip (SoC) design is divided into hi
 erarchical instances using the multiply-instantiated block (MIB) technique
  to simplify the design process. Top-level routing aims at providing routi
 ng prototyping between those instances. It requires consideration of repli
 cated routing paths that can either be utilized for routing or remain as f
 loating segments. Conventional path-searching based algorithm often fails 
 to find a legal solution under such a scenario. To address this, we propos
 e an effective and efficient top-level routing framework for MIBs by hashi
 ng the topology of each net and using a group maze routing scheme. Experim
 ental results demonstrate promising performance compared to the winners of
  the MIB-aware top-level router contest 2022 organized by Synopsys.\n\nTop
 ic: EDA\n\nKeyword: Physical Design and Verification\n\nSession Chairs: UD
 AY MALLAPPA (Intel Corporation) and Satish Sivaswamy (Advanced Micro Devic
 es (AMD))
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