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DTSTAMP:20240626T180034Z
LOCATION:3010\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240626T160000
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UID:dac_DAC 2024_sess144_RESEARCH1344@linklings.com
SUMMARY:Net Resource Allocation: A Desirable Initial Routing Step
DESCRIPTION:Research Manuscript\n\nZhisheng Zeng (State Key Lab of Process
 ors, Institute of Computing Technology, Chinese Academy of Sciences); Jika
 ng Liu (Shenzhen University); Zhipeng Huang (Peng Cheng Laboratory); Ye Ca
 i (Shenzhen University); Biwei Xie and Yungang Bao (State Key Lab of Proce
 ssors, Institute of Computing Technology, Chinese Academy of Sciences); an
 d Xingquan Li (Peng Cheng Laboratory)\n\nIn modern IC design, routing sign
 ificantly impacts chip performance, power, area, and design iteration coun
 t. Critical challenges in routing include generating  rectilinear Steiner 
 minimum tree (RSMT) for each net and handling routing resource among nets.
  Due to limited resources and net scale, congestion is inevitable in VLSI 
 circuit routing. Most competitive routers address congestion after routing
  without prior net guidance, leading to difficulty in managing resources a
 mong nets. To tackle routing and congestion, we suggest introducing a net 
 resource allocation step as a potentially desirable initial routing stage.
  Firstly, we introduce the concept of net region probability density (NRPD
 ) to achieve suitable net resource allocation. Using a prior NRPD, we mode
 l the resource allocation problem as quadratic programming (QP). We utiliz
 e penalty method to solve the QP quickly and obtain a posterior NRPD for e
 ach net on each grid. Based on the posterior NRPD and congestion map, we i
 ntroduce a cost scheme to guide net routing. This cost scheme supports a w
 eighted RSMT construction technique for better topological solutions. Addi
 tionally, we propose an iterative method for global routing and track assi
 gnment, improving detailed routing quality and optimizing design rule viol
 ations. Experimental results show the effectiveness of net resource alloca
 tion and demonstrate superior performance of our router over the OpenROAD'
 s router across multiple metrics.\n\nTopic: EDA\n\nKeyword: Physical Desig
 n and Verification\n\nSession Chairs: UDAY MALLAPPA (Intel Corporation) an
 d Satish Sivaswamy (Advanced Micro Devices (AMD))
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