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DTSTAMP:20240626T180033Z
LOCATION:3010\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240626T154500
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UID:dac_DAC 2024_sess144_RESEARCH1369@linklings.com
SUMMARY:Toward Controllable Hierarchical Clock Tree Synthesis with Skew-La
 tency-Load Tree
DESCRIPTION:Research Manuscript\n\nWeiguo Li (Minnan Normal University), Z
 hipeng Huang (Peng Cheng Laboratory), Bei Yu (The Chinese University of Ho
 ng Kong), Wenxing Zhu (Fuzhou University), and Xingquan Li (Peng Cheng Lab
 oratory)\n\nClock tree synthesis (CTS) constructs an efficient clock tree,
  meeting design constraints and minimizing resource usage. It serves as a 
 bridge between placement and routing, facilitating concurrent optimization
  of multiple design objectives. To construct a clock tree with lower laten
 cy and load capacitance while maintaining a specified skew constraint, we 
 introduce skew-latency-load tree (SLLT) which combines the merits of bound
  skew tree and Steiner shallow-light tree, along with an analysis and demo
 nstration of the boundaries of these two tree types. We propose a method f
 or constructing SLLT, which significantly reduces both the maximum latency
  and load capacitance compared to previous methods while ensuring skew con
 trol. Combining this routing topology generation method, we introduce a hi
 erarchical CTS framework, and it is constructed by integrating partition s
 chemes and buffering optimization techniques. We validate our solution at 
 28nm process technology, demonstrating superior performance compared to th
 e solutions of OpenROAD and advanced commercial tool. Our approach outperf
 orms in all metrics (max latency, skew, buffer number, clock capacitance),
  achieving a significant reduction in latency of 29.45% compared to OpenRO
 AD and 6.75% compared to the commercial tool.\n\nTopic: EDA\n\nKeyword: Ph
 ysical Design and Verification\n\nSession Chairs: UDAY MALLAPPA (Intel Cor
 poration) and Satish Sivaswamy (Advanced Micro Devices (AMD))
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